AT91M40800-33AI Atmel, AT91M40800-33AI Datasheet - Page 124

• Manufacturer Part Number: AT91M40800-33AI
• Description: IC ARM7 MCU 100 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M40800-33AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Clock Control
124
AT91X40 Series
The selected clock can be inverted with the CLKI bit in TC_CMR (Channel Mode). This
allows counting on the opposite edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The
BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note:
Figure 44. Clock Selection
The clock of each counter can be controlled in two different ways: it can be enabled/dis-
abled and started/stopped.
•
•
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
commands in the Control Register. In Capture Mode it can be disabled by an RB
load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled
by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the
start or the stop actions have no effect: only a CLKEN command in the Control
Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set
in the Status Register.
The clock can also be started or stopped: a trigger (software, synchro, external or
compare) always starts the clock. The clock can be stopped by an RB load event in
Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform
Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect
only if the clock is enabled.
In all cases, if an external clock is used, the duration of each of its levels must be longer
than the system clock (MCK) period. The external clock frequency must be at least 2.5
times lower than the system clock (MCK).
MCK/2
MCK/8
MCK/32
MCK/128
MCK/1024
XC0
XC1
XC2
1
CLKS
BURST
CLKI
Selected
Clock
1354D–ATARM–08/02