PIC16C924-08/SP Microchip Technology, PIC16C924-08/SP Datasheet - Page 71

• Manufacturer Part Number: PIC16C924-08/SP
• Description: IC MCU 64 LD 8MHZ 4K OTP 64-SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C924-08/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• For Use With: AC164025 - MODULE SKT PROMATEII 64DIPDVA16XP640 - ADAPTER DEVICE FOR MPLAB-ICE
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

Figure 11-13 and Figure 11-14 show Master-transmit-
ter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identical
to the start condition (SDA goes high-to-low while SCL
FIGURE 11-13: MASTER-TRANSMITTER SEQUENCE
FIGURE 11-14: MASTER-RECEIVER SEQUENCE
FIGURE 11-15: COMBINED FORMAT
Sr
A master reads a slave immediately after the first byte.
Transfer direction of data and acknowledgment bits depends on R/W bits.
Combined format - A master addresses a slave with a 10-bit address, then transmits
1997 Microchip Technology Inc.
For 7-bit address:
Combined format:
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
S
S
For 7-bit address:
Slave Address
S
From slave to master
From master to slave
Slave Address R/W A Data A Data A P
Slave Address R/W A Data A/A Sr
From slave to master
From master to slave
First 7 bits
Slave Address R/W A Data A Data A/A P
From slave to master
From master to slave
'1' (read)
'0' (write)
(write)
(read)
R/W A
data to this slave and reads data from this slave.
(n bytes - acknowledge)
(n bytes - acknowledge)
Slave Address
Second byte
data transferred
data transferred
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Sr = repeated
Start Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(n bytes + acknowledge)
(read or write)
Slave Address R/W A Data A/A
A
Data
A
(write)
Data A/A
For 10-bit address:
S
is high), but occurs after a data transfer acknowledge
pulse (not the bus-free state). This allows a master to
send “commands” to the slave and then receive the
requested information or to address a different slave
device. This sequence is shown in Figure 11-15.
For 10-bit address:
S
Slave Address
Direction of transfer
may change at this point
Slave Address
First 7 bits
A master transmitter addresses a slave receiver
First 7 bits
with a 10-bit address.
Sr Slave Address
A master transmitter addresses a slave receiver
with a 10-bit address.
Sr
Slave Address
(write)
Data A
First 7 bits
(write)
First 7 bits
P
R/W A1 Slave Address
R/W A1 Slave Address
(read)
(read)
Data
R/W A Data A
R/W A3
PIC16C9XX
Second byte
Second byte
A/A
P
Data A
DS30444E - page 71
A2
A2
Data
Data
A
A P
P