PIC16C72-10E/SP Microchip Technology, PIC16C72-10E/SP Datasheet - Page 157
![IC MCU OTP 2KX14 A/D PWM 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16C72-10E/SP
Manufacturer Part Number
PIC16C72-10E/SP
Description
IC MCU OTP 2KX14 A/D PWM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C72-04SO.pdf
(289 pages)
4.PIC16C72-04SO.pdf
(125 pages)
5.PIC16C72-04SO.pdf
(8 pages)
Specifications of PIC16C72-10E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C72-04SO PDF datasheet #3
- PIC16C72-04SO PDF datasheet #4
- PIC16C72-04SO PDF datasheet #5
- Current page: 157 of 289
- Download datasheet (3Mb)
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
OPTION
Operands:
Syntax:
Operation:
Status Affected: None
Encoding:
Description:
Words:
Cycles:
Example
1997 Microchip Technology Inc.
No Operation
[ label ]
None
No operation
None
No operation.
1
1
Load Option Register
[ label ]
None
(W)
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
1
1
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
Decode
NOP
Q1
00
00
OPTION
NOP
OPTION
Operation
0000
0000
Q2
No-
0110
Operation
0xx0
Q3
No-
0010
Operation
0000
No-
Q4
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
2nd Cycle
1st Cycle
Return from Interrupt
[ label ]
None
TOS
1
None
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by setting
Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
1
2
After Interrupt
Operation
Decode
RETFIE
Q1
00
No-
GIE
PC,
PIC16C7X
PC =
GIE =
RETFIE
Operation
Operation
0000
Q2
No-
No-
DS30390E-page 157
TOS
1
Operation
0000
Set the
GIE bit
Q3
No-
Operation
the Stack
Pop from
1001
Q4
No-
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