AT90S1200-4PC Atmel, AT90S1200-4PC Datasheet - Page 26

• Manufacturer Part Number: AT90S1200-4PC
• Description: IC MCU 1K FLSH 4MHZ LV 20DIP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S1200-4PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: POR, WDT
• Number Of I /o: 15
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Ram Size: -
• Data Converters: -

Prevent EEPROM
Corruption
26
AT90S1200
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When
address and data are correctly set up, the EEWE bit must be set to write the value into
the EEPROM. When the write access time (typically 2.5 ms at V
V
ware can poll this bit and wait for a zero before writing the next byte. When EEWE has
been set, the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal (EERE) is the read strobe to the EEPROM. When
the correct address is set up in the EEAR register, the EERE bit must be set. When the
EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register.
The EEPROM read access takes one instruction and there is no need to poll the EERE
bit. When EERE has been set, the CPU is halted for four cycles before the next instruc-
tion is executed.
Caution: If an interrupt routine accessing the EEPROM is interrupting another EEPROM
access, the EEAR or EEDR register will be modified, causing the interrupted EEPROM
access to fail. It is recommended to have the global interrupt flag cleared during
EEPROM write operation to avoid these problems.
During periods of low V
age is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board-level systems using the EEPROM, and the same design solutions
should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage for executing instructions is too low.
EEPROM data corruption can easily be avoided by following these design recommen-
dations (one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply
2. Keep the AVR core in Power-down Sleep mode during periods of low V
3. Store constants in Flash memory if the ability to change memory contents from
CC
voltage. This is best done by an external low V
referred to as a Brown-out Detector (BOD). Please refer to application note AVR
180 for design considerations regarding power-on reset and low-voltage
detection.
will prevent the CPU from attempting to decode and execute instructions, effec-
tively protecting the EEPROM registers from unintentional writes.
software is not required. Flash memory cannot be updated by the CPU, and will
not be subject to corruption.
= 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user soft-
CC
, the EEPROM data can be corrupted because the supply volt-
CC
Reset Protection circuit, often
CC
= 5V and 4 ms at
0838H–AVR–03/02
CC
. This