AT90LS8535-4JC Atmel, AT90LS8535-4JC Datasheet - Page 100
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AT90LS8535-4JC
Manufacturer Part Number
AT90LS8535-4JC
Description
IC MCU 8K 4MHZ A/D LV 44PLCC
Manufacturer
Atmel
Series
AVR® 90LSr
Specifications of AT90LS8535-4JC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Serial Programming
Algorithm
100
AT90S/LS8535
Figure 71. Serial Programming and Verify
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction
and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-
tion turns the content of every memory location in both the program and EEPROM
arrays into $FF.
The program and EEPROM memory arrays have separate address spaces: $0000 to
$0FFF for program memory and $0000 to $01FF for EEPROM memory.
Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low: > 2 XTAL1 clock cycles
High: > 2 XTAL1 clock cycles
When writing serial data to the AT90S8535, data is clocked on the rising edge of SCK.
When reading data from the AT90S8535, data is clocked on the falling edge of SCK.
See Figure 72, Figure 73 and Table 43 for timing details.
To program and verify the AT90SS8535 in the Serial Programming Mode, the following
sequence is recommended (see 4-byte instruction formats in Table 42 ):
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Program-
3. The serial programming instructions will not work if the communication is out of
Apply power between V
tal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the
XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held
low during power-up. In this case, RESET must be given a positive pulse of at least
two XTAL1 cycles duration after SCK has been set to “0”.
ming Enable serial instruction to the MOSI (PB5) pin.
synchronization. When in sync, the second byte ($53) will echo back when issu-
ing the third byte of the Programming Enable instruction. Whether the echo is
correct or not, all four bytes of the instruction must be transmitted. If the $53 did
not echo back, give SCK a positive pulse and issue a new Programming Enable
instruction. If the $53 is not seen within 32 attempts, there is no functional device
connected.
CLOCK INPUT
GND
CC
and GND while RESET and SCK are set to “0”. If a crys-
GND
RESET
XTAL1
AT90S8535
VCC
PB6
PB5
PB7
2.7 - 6.0V
SCK
MISO
MOSI
1041H–11/01