AT90LS2333-4AI Atmel, AT90LS2333-4AI Datasheet - Page 36

• Manufacturer Part Number: AT90LS2333-4AI
• Description: IC MCU 2K 4MHZ A/D LV IT 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS2333-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 15. PWM Outputs OCR = $0000 or TOP
In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter changes direction at $0000. Timer Overflow
Interrupt1 operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV1 is set provided that Timer
Overflow Interrupt1 and global interrupts are enabled. This also applies to the Timer Output Compare1 flag and interrupt.
Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the
Watchdog reset interval can be adjusted as shown in Table 6. See characterization data for typical values at other V
els. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. Eight different clock cycle periods can be
selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S2333/4433
resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 22.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is dis-
abled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 35. Watchdog Timer
Watchdog Timer Control Register - WDTCR
•
These bits are reserved bits in the AT90S2333/4433 and will always read as zero.
•
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware
will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
36
Bit
$21 ($41)
Read/Write
Initial value
Bits 7..5 - Res: Reserved bits
Bit 4 - WDTOE: Watch Dog Turn-Off Enable
COM11
1
1
1
1
AT90S/LS2333 and AT90S/LS4433
R
7
0
-
R
6
0
-
COM10
0
0
1
1
R
5
0
-
WDTOE
R/W
4
0
WDE
R/W
OCR1
$0000
$0000
3
0
TOP
TOP
WDP2
R/W
2
0
WDP1
R/W
1
0
WDP0
R/W
0
0
Output OC1
WDTCR
H
H
L
L
CC
lev-