PIC17C756/CL Microchip Technology, PIC17C756/CL Datasheet - Page 69
PIC17C756/CL
Manufacturer Part Number
PIC17C756/CL
Description
MICRO CTRL 16K MEMORY EPROM 68CL
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756/CL
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-CLCC Window, 68-CERQUAD
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC17C756/CL
Manufacturer:
MICROCH
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 69 of 321
- Download datasheet (3Mb)
Example 10-2 shows an instruction sequence to initial-
ize PORTB. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
FIGURE 10-6: BLOCK DIAGRAM OF RB3:RB2 PORT PINS
1997 Microchip Technology Inc.
Note: I/O pins have protection diodes to V
Weak
Pull-Up
OE
DD
and Vss.
Port
Input Latch
Port
Data
Preliminary
Q
EXAMPLE 10-2: INITIALIZING PORTB
MOVLB
CLRF
MOVLW
MOVWF
CK
D
PORTB
0xCF
DDRB
0
; Select Bank 0
; Initialize PORTB by clearing
;
; Value used to initialize
;
; Set RB<3:0> as inputs
;
;
Match Signal
from other
port pins
Q
output data latches
data direction
R
RB<5:4> as outputs
RB<7:6> as inputs
CK
D
RBPU
Peripheral Data in
DS30264A-page 69
Peripheral_enable
WR_PORTB (Q4)
Peripheral_output
RD_PORTB (Q2)
WR_DDRB (Q4)
RD_DDRB (Q2)
(PORTA<7>)
Data Bus
RBIF
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