PIC17C756/CL Microchip Technology, PIC17C756/CL Datasheet - Page 239
PIC17C756/CL
Manufacturer Part Number
PIC17C756/CL
Description
MICRO CTRL 16K MEMORY EPROM 68CL
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756/CL
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-CLCC Window, 68-CERQUAD
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC17C756/CL
Manufacturer:
MICROCH
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 239 of 321
- Download datasheet (3Mb)
FIGURE 20-11: SPI SLAVE MODE TIMING (CKE = 0)
TABLE 20-11: SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
1997 Microchip Technology Inc.
*
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
Param.
SCK
(CKP = 0)
(CKP = 1)
SDO
SDI
SDI
SS
SCK
No.
Characterized but not tested.
70
71
72
73
74
75
76
77
78
79
80
83
tested.
Refer to Figure 20-1 for load conditions.
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ
TscR
TscF
TscH2doV,
TscL2doV
TscH2ssH,
TscL2ssH
Sym
70
80
Characteristic
SS to SCK or SCK input
SCK input high time (slave mode)
SCK input low time (slave mode)
Setup time of SDI data input to SCK
edge
Hold time of SDI data input to SCK
edge
SDO data output rise time
SDO data output fall time
SS to SDO output hi-impedance
SCK output rise time (master mode)
SCK output fall time (master mode)
SDO data output valid after SCK
edge
SS
71
after SCK edge
73
MSB IN
MSB
74
72
75, 76
Preliminary
BIT6 - - - - - -1
BIT6 - - - -1
T
T
CY
CY
1.5T
+ 40 *
T
100 *
100 *
10 *
Min
CY
—
—
—
—
—
78
+ 20 *
+ 20 *
79
CY
*
Typ†
LSB
79
—
—
—
—
—
10
10
—
10
10
—
—
78
LSB IN
83
Max
25 *
25 *
50 *
25 *
50 *
25 *
—
—
—
—
—
—
77
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS30264A-page 239
Conditions
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