SAK-TC1797-512F180E AC Infineon Technologies, SAK-TC1797-512F180E AC Datasheet - Page 26

• Manufacturer Part Number: SAK-TC1797-512F180E AC
• Description: IC MCU 32BIT FLASH 416-BGA
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1797-512F180E AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 219
• Program Memory Size: 4MB (4M x 8)
• Program Memory Type: FLASH
• Ram Size: 224K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 48x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 180.0 MHz
• Sram (incl. Cache): 224.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 48
• Program Memory: 4.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000432392

2.3.4
The following SCU introduction gives an overview about the TC1797 System Control
Unit (SCU) For Information about the SCU see chapter 3.
2.3.4.1
The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1797.
During user program execution the frequency can be programmed for an optimal ratio
between performance and power consumption.
2.3.4.2
The main features of the WDT are summarized here.
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2.3.4.3
The following reset request triggers are available:
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There are two basic types of reset request triggers:
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Data Sheet
16-bit Watchdog counter
Selectable input frequency:
16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
Incorporation of the ENDINIT bit and monitoring of its modifications
Sophisticated Password Access mechanism with fixed and user-definable password
fields
Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation
Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation
Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled
Double Reset Detection
1 External power-on hardware reset request trigger; PORST, (cold reset)
2 External System Request reset triggers; ESR0 and ESR1,(warm reset)
Watchdog Timer (WDT) reset request trigger, (warm reset)
Software reset (SW), (warm reset)
Debug (OCDS) reset request trigger, (warm reset)
Resets via the JTAG interface
Trigger sources that do not depend on a clock, such as the PORST. This trigger force
the device into an asynchronous reset assertion independently of any clock. The
activation of an asynchronous reset is asynchronous to the system clock, whereas
its de-assertion is synchronized.
System Control Unit
Clock Generation Unit
Features of the Watchdog Timer
Reset Operation
f
FPI
/256 or
f
22
FPI
/16384
Introduction
V1.1, 2009-04
TC1797