DS5003FPM-16+ Maxim Integrated Products, DS5003FPM-16+ Datasheet - Page 14

• Manufacturer Part Number: DS5003FPM-16+
• Description: IC MICROPROCESSOR SECURE 80-MQFP
• Manufacturer: Maxim Integrated Products
• Series: DS500xr

Specifications of DS5003FPM-16+

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: SRAM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-MQFP, 80-PQFP
• Processor Series: DS5003
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB, 64 KB, 128 KB
• Data Ram Size: 32 KB, 64 KB, 128 KB
• Interface Type: UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Secure Microprocessor Chip
14
47, 48
68, 73
______________________________________________________________________________________
PIN
62
78
22
23
14
34
32
42
43
53
3
XTAL2,
NAME
XTAL1
PROG
MSEL
VRST
N.C.
CE4
RST
PE1
PE2
PE3
PE4
SDI
PF
Active-Low Chip-Enable 4. This chip enable is provided to access a fourth 32kB block of
memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is
unused. CE4 is lithium-backed and remains at a logic-high when V
Active-Low Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh
when the PES bit is set to logic 1. Commonly used to chip enable a byte-wide real-time clock
such as the DS1283. PE1 is lithium backed and remains at a logic-high when V
V
Active-Low Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh
when the PES bit is set to logic 1. PE2 is lithium backed and remains at a logic-high when V
falls below V
Active-Low Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh
when the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V
Active-Low Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh
when the PES bit is set to logic 1. PE4 is not lithium backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V
Memory Select. This signal controls the memory size selection. When MSEL = +5V, the
DS5003 expects to use 32kB x 8 SRAMs. When MSEL = 0V, the DS5003 expects to use a
128kB x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
Crystal Connections. Used to connect an external crystal to the internal oscillator. XTAL1 is the
input to an inverting amplifier and XTAL2 is the output.
Active-High Reset Input. A logic 1 applied to this pin activates a reset state. This pin is pulled
down internally so this pin can be left unconnected if not used. An RC power-on reset circuit is
not needed and is not recommended.
Invokes the Bootstrap Loader on Falling Edge. This signal should be debounced so that only
one edge is detected. If connected to ground, the microcontroller enters bootstrap loading on
power-up. This signal is pulled up internally.
Reset State Active Due to Low V
the power supply (V
state. When this occurs, the DS5003 drives this pin to logic 0. Because the microcontroller is
lithium backed, this signal is guaranteed even when V
forces a reset if pulled low externally. This allows multiple parts to synchronize their power-
down resets.
Lithium Backup Active. This output goes to a logic 0 to indicate that the microcontroller has
switched to lithium backup. This corresponds to V
lithium backed, this signal is guaranteed even when V
signal is to control lithium-powered current to isolate battery-backed functions from nonbattery-
backed functions.
Self-Destruct Input. An active high on this pin causes an unlock procedure. This results in the
destruction of vector SRAM, encryption keys, and the loss of power from V
be grounded if not used.
No Connection
LI
. Connect PE1 to battery-backed circuitry only.
RESET, STATUS, AND SELF-DESTRUCT PINS
LI
. Connect PE2 to battery-backed circuitry only.
CC
MISCELLANEOUS PINS
) has fallen below the V
CLOCK PINS
CC
. This I/O pin (open drain with internal pullup) indicates that
FUNCTION
CCMIN
Pin Description (continued)
CC
level and the microcontroller is in a reset
CC
CC
< V
CC
CC
< V
< V
LI
= 0V. Because it is an I/O pin, it also
= 0V. The normal application of this
. Because the microcontroller is
LI
LI
.
.
CC
falls below V
CCO
. This pin should
CC
falls below
LI
.
CC