SAK-TC1762-128F66HL AC Infineon Technologies, SAK-TC1762-128F66HL AC Datasheet - Page 33

• Manufacturer Part Number: SAK-TC1762-128F66HL AC
• Description: IC MCU 32BIT 1024KB FLSH 176LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1762-128F66HL AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 66.0 MHz
• Sram (incl. Cache): 52.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Preliminary
3.5
The DMA Controller of the TC1762 transfers data from data source locations to data
destination locations without intervention of the CPU or other on-chip devices. One data
move operation is controlled by one DMA channel. Eight DMA channels are provided in
one DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Block to
the two FPI Bus interfaces and an MLI bus interface. In the TC1762, the FPI Bus
interfaces are connected to the System Peripheral Bus and the DMA Bus. The third
specific bus interface provides a connection to the Micro Link Interface module (MLI0 in
the TC1762) and other DMA-related devices (Memory Checker module in the TC1762).
Clock control, address decoding, DMA request wiring, and DMA interrupt service request
control are implementation-specific and managed outside the DMA controller kernel.
Figure 3-1
Figure 3-1
Features
•
Data Sheet
8 independent DMA channels
Requests
Decoder
Interrupt
Request
On-chip
Address
Control
Periph.
Nodes
Clock
Units
DMA
of
DMA Controller and Memory Checker
shows the implementation details and interconnections of the DMA module.
SR[15:0]
DMA Controller Block Diagram
f
DMA
CH0n_OUT
Selection/
Arbitration
Request
DMA Interrupt Control
DMA Sub-Block 0
DMA Controller
Transaction
Control Unit
Channels
00-07
DMA
29
Arbiter/
Control
Switch
Switch
Bus
Functional Description
V1.0, 2008-04
System
Periphera
Bus
DMA Bus
Checker
Memory
MCB06149
MLI0
TC1762