SAF-XC164N-32F40F BB Infineon Technologies, SAF-XC164N-32F40F BB Datasheet - Page 61

• Manufacturer Part Number: SAF-XC164N-32F40F BB
• Description: IC MCU 16BIT FLASH 100-TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164N-32F40F BB

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Packages: PG-TQFP-100
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 12.0 KByte
• Program Memory: 256.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: SP000277080

4.3.2
The XC164N’s Flash module delivers data within a fixed access time (see
Accesses to the Flash module are controlled by the PMI and take 1 + WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time
available speed grade as well as on the actual system frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
Table 15
Parameter
Flash module access time (Standard)
Programming time per 128-byte block
Erase time per sector
1) The actual access time is also influenced by the system frequency, so the frequency ranges are not fully linear.
2) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), Standard devices
must be operated with 2 waitstates: ((2 + 1) × 25 ns) ≥ 70 ns.
Table 16
Table 16
Required Waitstates
0 WS (WSFLASH = 00
1 WS (WSFLASH = 01
2 WS (WSFLASH = 10
Note: The maximum achievable system frequency is limited by the properties of the
Data Sheet
See
t
ACC
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5% … 15%.
respective derivative, i.e. 40 MHz (or 20 MHz for xxx-32F20F devices).
Table 16
indicates the interrelation of waitstates, system frequency, and speed grade.
of the Flash array. Therefore, the required Flash waitstates depend on the
On-chip Flash Operation
.
Flash Characteristics (Operating Conditions apply)
Flash Access Waitstates
B
B
B
)
)
)
59
Symbol
t
t
t
ACC
PR
ER
Frequency Range for Standard Flash
Speed
f
f
f
CPU
CPU
CPU
CC
CC
CC
≤ 16 MHz
≤ 28 MHz
≤ 40 MHz
Min.
–
–
–
Limit Values
Electrical Parameters
Typ.
2
–
200
2)
2)
Max.
70
5
500
Derivatives
XC164N-32
Table 15
V1.0, 2006-08
1)
Unit
ns
ms
ms
).