SAK-XC2265N-40F80L Infineon Technologies, SAK-XC2265N-40F80L Datasheet - Page 110

• Manufacturer Part Number: SAK-XC2265N-40F80L
• Description: IC MCU 16BIT FLASH 100-LQFP
• Manufacturer: Infineon Technologies
• Series: XC22xxNr

Specifications of SAK-XC2265N-40F80L

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 320KB (320K x 8)
• Program Memory Type: FLASH
• Ram Size: 34K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LSQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000527774

Variable Memory Cycles
External bus cycles of the XC226xN are executed in five consecutive cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module
using the READY handshake input.
This table provides a summary of the phases and the ranges for their length.
Table 31
Bus Cycle Phase
Address setup phase, the standard duration of this
phase (1 … 2 TCS) can be extended by 0 … 3 TCS
if the address window is changed
Command delay phase
Write Data setup/MUX Tristate phase
Access phase
Address/Write Data hold phase
Note: The bandwidth of a parameter (from minimum to maximum value) covers the
Note: Operating Conditions apply.
Table 32
voltage_range= upper
Table 32
Parameter
Output valid delay for RD,
WR(L/H)
Output valid delay for
BHE, ALE
Address output valid delay
for A23 ... A0
Data Sheet
whole operating range (temperature, voltage) as well as process variations. Within
a given device, however, this bandwidth is smaller than the specified range. This
is also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
is valid under the following conditions:
Programmable Bus Cycle Phases (see timing diagrams)
External Bus Timing for Upper Voltage Range
XC2261N, XC2263N, XC2264N, XC2265N, XC2268N
Symbol
t
t
t
10
11
12
CC
CC
CC
Min.
−
−
−
110
Values
Typ.
7
7
8
C
tpD
Parameter Valid Values Unit
tpAB
tpC
tpE
tpF
L
= 20 pF; voltage_range= upper ;
XC2000 Family / Value Line
Max.
13
14
14
Unit Note /
ns
ns
ns
Electrical Parameters
1 … 2 (5)
0 … 3
0 … 1
1 … 32
0 … 3
Test Condition
V1.3, 2010-04
TCS
TCS
TCS
TCS
TCS