UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 479
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UPD78F1146AGB-GAH-AX
Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1146AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(3) SO latch
(4) Wakeup controller
(5) Prescaler
(6) Serial clock counter
(7) Interrupt request signal generator
(8) Serial clock controller
(9) Serial clock wait controller
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
(11) Data hold time correction circuit
(12) Start condition generator
(13) Stop condition generator
The SO latch is used to retain the SDA0 pin’s output level.
This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the
address value set to slave address register 0 (SVA0) or when an extension code is received.
This selects the sampling clock to be used.
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
This circuit controls the generation of interrupt request signals (INTIIC0).
An I
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit)
• Interrupt request generated when a stop condition is detected (set by SPIE0 bit)
Remark
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
This circuit controls the wait timing.
These circuits generate and detect each status.
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
This circuit generates a start condition when the STT0 bit is set to 1.
However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released
(IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1.
This circuit generates a stop condition when the SPT0 bit is set to 1.
2
C interrupt request is generated by the following two triggers.
WTIM0 bit: Bit 3 of IIC control register 0 (IICC0)
SPIE0 bit: Bit 4 of IIC control register 0 (IICC0)
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
477
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