UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 467
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UPD78F1146AGB-GAH-AX
Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1146AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes 1. When changing the clock selected for f
Remark
Register
SMR02
CKS02
0
1
2. SAU can be operated at a fixed division ratio of the subsystem clock, regardless of the f
(CKC) value), do so after having stopped (ST0 = 000FH) the operation of the serial array
unit (SAU). When selecting INTTM02 for the operation clock, also stop the timer array unit
(TAU) (TT0 = 00FFH).
frequency (main system clock, subsystem clock), by operating the interval timer for which
f
the TIS0 register to 1) and selecting INTTM02 and INTTM03 by using the SPSm register in
channels 2 and 3 of TAU. When changing f
described in Note 1 above.
SUB
PRS
013
X: Don’t care
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
/4 has been selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of
PRS
012
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
Table 11-4 Operating Clock Selection
Other than above
PRS
011
CHAPTER 11 SERIAL ARRAY UNIT
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
1
SPS0 Register
User’s Manual U17854EJ9V0UD
PRS
010
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
PRS
003
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
PRS
002
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
PRS
001
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
1
CLK
CLK
PRS
(by changing the system clock control register
000
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
, however, SAU and TAU must be stopped as
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02
Setting prohibited
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Operation Clock (MCK)
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
8
9
10
11
2
3
4
5
6
7
8
9
10
11
Note 2
Note 2
f
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
CLK
= 20 MHz
Note 1
465
CLK
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