UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 751
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UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(3) Serial interface: IIC0
Notes 1.
Remark CL00, CL01, DFC0: Bits 0, 1, and 2 of the IIC clock select register 0 (IICCL0)
SDA0
SCL0
SCL0 clock frequency
Setup time of restart condition
Hold time
Hold time when SCL0 = “L”
Hold time when SCL0 = “H”
Data setup time (reception)
Data hold time (transmission)
Setup time of stop condition
Bus-free time
(T
(a) IIC0
A
2.
3. When 3.2 MHz ≤ f
4. When 6.7 MHz ≤ f
5. When 2.0 MHz ≤ f
6. When 4.0 MHz ≤ f
7. When 8.0 MHz ≤ f
8. When 7.6 MHz ≤ f
Stop
condition
= −40 to +85°C, 1.8 V ≤ V
Parameter
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of t
(acknowledge) timing.
t
LOW
Start
condition
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
t
HD:STA
t
LOW
Note 2
Note 1
CLK
CLK
CLK
CLK
CLK
CLK
t
HD:DAT
≤ 4.19 MHz.
≤ 8.38 MHz.
< 3.2 MHz. At this time, use the SCL0 clock within 85 kHz.
< 6.7 MHz. At this time, use the SCL0 clock within 340 kHz.
≤ 16.76 MHz.
< 8.0 MHz.
f
t
t
t
t
t
t
t
t
DD
SCL
SU:STA
HD:STA
LOW
HIGH
SU:DAT
HD:DAT
SU:STO
BUF
Symbol
= EV
DD
6.7 MHz ≤ f
4.0 MHz ≤ f
3.2 MHz ≤ f
2.0 MHz ≤ f
CL00 = 1 and CL01 = 1
CL00 = 0 and CL01 = 0, or
CL00 = 1 and CL01 = 0
CL00 = 0 and CL01 = 1
≤ 5.5 V, V
HD:DAT
User’s Manual U17854EJ9V0UD
IIC0 serial transfer timing
t
HIGH
t
SU:DAT
is during normal transfer and a wait state is inserted in the ACK
Conditions
SS
CLK
CLK
CLK
CLK
= EV
< 6.7 MHz
< 4.0 MHz
< 3.2 MHz
SS
t
SU:STA
= AV
SS
Restart
condition
= 0 V)
Standard Mode
MIN.
250
4.7
4.0
4.7
4.0
4.0
4.7
0
0
0
0
0
0
0
t
HD:STA
3.45
5.50
MAX.
3.45
3.45
100
100
100
85
Note 3
Note 5
MIN.
100
0.6
0.6
1.3
0.6
0.6
1.3
0
0
−
−
0
0
0
Fast Mode
Standard Products
t
SU:STO
0.95
0.9
1.5
0.9
MAX.
340
400
0.9
−
−
Note 4
Note 6
Note 7
Note 8
Stop
condition
Unit
kHz
kHz
kHz
kHz
μ
μ
μ
μ
ns
μ
μ
μ
μ
μ
μ
μ
749
s
s
s
s
s
s
s
s
s
s
s
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