UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 485
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UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 485 of 880
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Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition
Caution When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1 during the
Remark
Cautions concerning set timing
• For master reception:
• For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore,
• Cannot be set to 1 at the same time as STT0.
• SPT0 can be set to 1 only when in master mode
• When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks,
• Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT0 = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
note that a stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be
changed from 0 to 1 during the wait period following the output of eight clocks, and SPT0 should be set to 1 during
the wait period that follows the output of the ninth clock.
SPT0
0
1
generated before the first stop condition is detected following the switch to the operation enabled
status.
ninth clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to
high impedance.
Bit 0 (SPT0) becomes 0 when it is read after data setting.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high
level. Next, after the rated amount of time has elapsed, the SDA0 line changes from low level to high level
and a stop condition is generated.
Figure 12-6. Format of IIC Control Register 0 (IICC0) (4/4)
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave
has been notified of final reception.
set it during the wait period that follows output of the ninth clock.
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
Note
.
Stop condition trigger
Condition for setting (SPT0 = 1)
• Set by instruction
483
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