UPD78F1142AGK-GAJ-AX Renesas Electronics America, UPD78F1142AGK-GAJ-AX Datasheet - Page 871
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UPD78F1142AGK-GAJ-AX
Manufacturer Part Number
UPD78F1142AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6th edition
Edition
Addition of Notes 3 to Figure 5-6 Format of System Clock Control Register (CKC)
Addition of Cautions 5 to Figure 5-8. Format of Operation Speed Mode Control
Register (OSMC)
Change of Table 6-1. Configuration of Timer Array Unit
Deletion of bit 7 (TOM07) of TOM0 register
Change of description of MASTER0n bit in Figure 6-6. Format of Timer Mode
Register 0n (TMR0n) (1/3)
Change of Figure 6-16. Format of Timer Input Select Register 0 (TIS0) and
Caution
Addition of description to 6.3 (10) Timer output register 0 (TO0)
Addition of description to 6.3 (12) Timer output mode register 0 (TOM0)
Change of Remark in Figure 6-20. Format of Timer Output Mode Register 0
(TOM0)
Change of Remark in Figure 6-21. Format of Input Switch Control Register (ISC)
Change of Cautions 1 in Figure 7-2. Format of Peripheral Enable Register 0
(PER0)
Addition of description to 7.3 (15) Alarm hour register (ALARMWH)
Addition of Note to Figure 7-18. Procedure for Starting Operation of Real-Time
Counter
Change of Cautions 1 and Cautions 2 in 8.3 (1) Watchdog timer enable register
(WDTE)
Change of SOm register
Change of Figure 11-1. Block Diagram of Serial Array Unit 0
Change of Figure 11-2. Block Diagram of Serial Array Unit 1
Change of description in 11.3 (12) Serial output register m (SOm)
Addition of 11.4 Operation stop mode
Change of Figure 11-27. Procedure for Resuming Master Transmission
Change of Figure 11-36. Timing Chart of Master Reception (in Single-Reception
Mode)
Change of Figure 11-41. Procedure for Resuming Master
Transmission/Reception
Change of Figure 11-42. Timing Chart of Master Transmission/Reception (in
Single-Transmission/Reception Mode)
Change of Figure 11-44. Timing Chart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Figure 11-45. Flowchart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Figure 11-49. Procedure for Resuming Slave Transmission
Change of Figure 11-50. Timing Chart of Slave Transmission (in Single-
Transmission Mode)
Change of Figure 11-57. Procedure for Resuming Slave Reception
Change of Figure 11-58. Timing Chart of Slave Reception (in Single-Reception
Mode)
Change of Figure 11-63. Procedure for Resuming Slave Transmission/Reception
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
Description
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER 8
WATCHDOG TIMER
CHAPTER 11 SERIAL
ARRAY UNIT
Chapter
(7/15)
869
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