UPD78F1142AGK-GAJ-AX Renesas Electronics America, UPD78F1142AGK-GAJ-AX Datasheet - Page 300
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UPD78F1142AGK-GAJ-AX
Manufacturer Part Number
UPD78F1142AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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298
Note
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
Remarks 1. n = 0, 1
Address: FFFA5H
Symbol
CKSn
Setting an output clock exceeding 10 MHz is prohibited when 2.7 V ≤ V
MHz at V
2. If the selected clock (f
2. f
3. f
PCLOEn
PCLOEn
becomes undefined.
MAIN
SUB
CSELn
DD
<7>
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
< 2.7 V is also prohibited.
: Subsystem clock frequency
: Main system clock frequency
After reset: 00H
Figure 9-2. Format of Clock Output Select Register n (CKSn)
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Output disable (default)
Output enable
CCSn2
6
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R/W
CCSn1
MAIN
User’s Manual U17854EJ9V0UD
5
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
or f
PCLBUZn output enable/disable specification
SUB
CCSn0
) stops during clock output (PCLOEn = 1), the output
4
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
CSELn
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
3
2
3
4
5
6
7
2
3
4
11
12
13
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
2.44 kHz
1.22 kHz
610 Hz
PCLBUZn output clock selection
5 MHz
f
MAIN
CCSn2
=
2
DD
. Setting a clock exceeding 5
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
4.88 kHz
2.44 kHz
1.22 kHz
32.768 kHz
16.384 kHz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
10 MHz
512 Hz
256 Hz
f
MAIN
CCSn1
Note
1
=
5 MHz
1.25 MHz
9.76 kHz
4.88 kHz
2.44 kHz
Setting
prohibited
10 MHz
2.5 MHz
20 MHz
f
CCSn0
MAIN
0
Note
=
Note
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