UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 571
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UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Remark
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA0 (INTDMA0), set DST0 to 0 and then DEN0 to 0 (for details, refer to
14.5.7 Forcible termination by software).
Figure 14-11. Setting Example of UART Consecutive Reception + ACK Transmission
This is an example where a software trigger is used as a DMA start source.
If ACK is not transmitted and if only data is consecutively received from UART, the UART reception
end interrupt (INTSR0) can be used to start DMA for data reception.
Setting for UART reception
DRA0 = FE00H
DBC0 = 0040H
User program
DMC0 = 00H
DSA0 = 12H
processing
DEN0 = 1
DST0 = 1
Start
CHAPTER 14 DMA CONTROLLER
DEN0 = 0
DST0 = 0
INTSR0 occurs.
RETI
User’s Manual U17854EJ9V0UD
End
INTDMA0
occurs.
Note
INTSR0 interrupt routine
DMA0 transfer
STG0 = 1
P10 = 1
P10 = 0
RETI
Hardware operation
569
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