UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 504
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UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
UPD78F1142AGB-GAH-AX
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12.5.10 Address match detection method
address.
address register 0 (SVA0) matches the slave address sent by the master device, or when an extension code has been
received.
12.5.11 Error detection
(IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data
to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match.
12.5.12 Extension code
502
In I
Address match can be detected automatically by hardware. An INTIIC0 occurs when the address set to the slave
In I
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
2
2
C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
(EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge
of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected.
when SVA0 is set to 11110xx0. Note that INTIIC0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC0 = 1
• Seven bits of data match:
Remark
code, such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next
communication operation.
Remark
Slave Address
0 0 0 0 0 0 0
1 1 1 1 0 x x
1 1 1 1 0 x x
EXC0: Bit 5 of IIC status register 0 (IICS0)
COI0: Bit 4 of IIC status register 0 (IICS0)
See the I
other than those described above.
2
Table 12-5. Bit Definitions of Major Extension Codes
C bus specifications issued by NXP Semiconductors for details of extension codes
R/W Bit
CHAPTER 12 SERIAL INTERFACE IIC0
0
0
1
COI0 = 1
User’s Manual U17854EJ9V0UD
General call address
10-bit slave address specification (during address
authentication)
10-bit slave address specification (after address match, when
read command is issued)
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