UPD78F1142AGA-HAB-AX Renesas Electronics America, UPD78F1142AGA-HAB-AX Datasheet - Page 394
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UPD78F1142AGA-HAB-AX
Manufacturer Part Number
UPD78F1142AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.5.4 Slave transmission
input from another device.
392
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
Slave transmission is that the 78K0R/KE3 transmits data to another device in the state of a transfer clock being
Notes 1. Because the external serial clock input to pins SCK00, SCK10 is sampled internally and used, the fastest
Remarks 1. f
3-Wire Serial I/O
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 27
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
transfer rate is f
2. n: Channel number (n = 0, 2)
MCK
: Operation clock (MCK) frequency of target channel
Channel 0 of SAU0
SCK00, SO00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVF0n) only
7 or 8 bits
Max. f
Selectable by DAP0n bit
• DAP0n = 0: Data output starts from the start of the operation of the serial clock.
• DAP0n = 1: Data output starts half a clock before the start of the serial clock operation.
Selectable by CKP0n bit
• CKP0n = 0: Forward
• CKP0n = 1: Reverse
MSB or LSB first
MCK
MCK
/6 [Hz].
/6 [Hz]
Notes 1, 2
CHAPTER 11 SERIAL ARRAY UNIT
CSI00
User’s Manual U17854EJ9V0UD
ELECTRICAL SPECIFICATIONS (STANDARD
Channel 2 of SAU0
SCK10, SO10
INTCSI10
CSI10
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