UPD78F1142AGA-HAB-AX Renesas Electronics America, UPD78F1142AGA-HAB-AX Datasheet - Page 378
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1142AGA-HAB-AX
Manufacturer Part Number
UPD78F1142AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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<R>
11.5.2 Master reception
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
Remark
376
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
Master reception is that the 78K0R/KE3 outputs a transfer clock and receives data from other device.
3-Wire Serial I/O
specifications (see CHAPTER 27
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
n: Channel number (n = 0, 2)
Channel 0 of SAU0
SCK00, SI00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVF0n) only
7 or 8 bits
Max. f
Selectable by DAP0n bit
• DAP0n = 0: Data input starts from the start of the operation of the serial clock.
• DAP0n = 1: Data input starts half a clock before the start of the serial clock operation.
Selectable by CKP0n bit
• CKP0n = 0: Forward
• CKP0n = 1: Reverse
MSB or LSB first
CLK
/4 [Hz], Min. f
CHAPTER 11 SERIAL ARRAY UNIT
CSI00
CLK
User’s Manual U17854EJ9V0UD
/(2 × 2
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
11
× 128) [Hz]
Note
f
CLK
Channel 2 of SAU0
SCK10, SI10
INTCSI10
: System clock frequency
CSI10
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