MAXQ622G-0000+ Maxim Integrated Products, MAXQ622G-0000+ Datasheet - Page 29

IC MCU 16BIT 64K IR MOD 64LQFP

MAXQ622G-0000+

Manufacturer Part Number
MAXQ622G-0000+
Description
IC MCU 16BIT 64K IR MOD 64LQFP
Manufacturer
Maxim Integrated Products
Series
MAXQ™r
Datasheet

Specifications of MAXQ622G-0000+

Core Processor
RISC
Core Size
16-Bit
Speed
12MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, Infrared, Power-Fail, POR, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
MAXQ622
Core
RISC
Data Bus Width
16 bit
Data Ram Size
6 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
44
Number Of Timers
2
Operating Supply Voltage
1.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MAXQUSBJTAG-KIT MAXQ622-KIT
Minimum Operating Temperature
0 C
For Use With
MAXQ622-KIT# - EVALUATION KIT FOR MAXQ622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Table 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
(continued)
The low-power, high-performance RISC architecture of
this device makes it an excellent fit for many portable
or battery-powered applications. It is ideally suited for
applications such as universal remote controls that
require the cost-effective integration of IR transmit/
receive capability.
Careful PCB layout significantly minimizes system-level
digital noise that could interact with the microcontroller
or peripheral components. The use of multilayer boards
is essential to allow the use of dedicated power planes.
The area under any digital components should be a con-
tinuous ground plane if possible. Keep bypass capacitor
leads short for best noise rejection and place the capaci-
tors as close to the leads of the devices as possible.
CMOS design guidelines for any semiconductor require
that no pin be taken above V
of this guideline can result in a hard failure (damage to
the silicon inside the device) or a soft failure (uninten-
tional modification of memory contents). Voltage spikes
above or below the device’s absolute maximum ratings
can potentially cause a devastating IC latchup.
Microcontrollers commonly experience negative volt-
age spikes through either their power pins or general-
STATE
D
E
F
POWER-FAIL
(Periodically)
Applications Information
Off
On
Off
______________________________________________________________________________________
Grounds and Bypassing
REGULATOR
DD
INTERNAL
or below GND. Violation
Infrared Module and Optional USB
Off
Off
Off
OSCILLATOR
CRYSTAL
16-Bit Microcontrollers with
Off
Off
Off
purpose I/O pins. Negative voltage spikes on power pins
are especially problematic as they directly couple to the
internal power buses. Devices such as keypads can
conduct electrostatic discharges directly into the micro-
controller and seriously damage the device. System
designers must protect components against these tran-
sients that can corrupt system memory.
Designers must have the following documents to fully
use all the features of this device. This data sheet
contains pin descriptions, feature overviews, and elec-
trical specifications. Errata sheets contain deviations
from published specifications. The user’s guides offer
detailed information about device features and opera-
tion. The following documents can be downloaded from
www.maxim-ic.com/microcontrollers.
• This MAXQ612/MAXQ622 data sheet, which contains
• The MAXQ612 /MAXQ622 revision-specific errata sheet
• The MAXQ622 User’s Guide, which contains detailed
RETENTION
electrical/timing specifications and pin descriptions.
(www.maxim-ic.com/errata).
information on features and operation, including pro-
gramming.
SRAM
Yes
Yes
Additional Documentation
Application enters stop mode.
V
CPU in stop mode.
V
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail, and puts CPU in reset.
Power-fail monitor is turned on periodically.
V
Device held in reset. No operation allowed.
DD
POR
DD
> V
< V
< V
RST
POR
DD
.
.
< V
COMMENTS
RST
.
29

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