MAXQ622G-0000+ Maxim Integrated Products, MAXQ622G-0000+ Datasheet - Page 22

• Manufacturer Part Number: MAXQ622G-0000+
• Description: IC MCU 16BIT 64K IR MOD 64LQFP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ622G-0000+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, Infrared, Power-Fail, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: MAXQ622
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• Operating Supply Voltage: 1.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MAXQUSBJTAG-KIT MAXQ622-KIT
• Minimum Operating Temperature: 0 C
• For Use With: MAXQ622-KIT# - EVALUATION KIT FOR MAXQ622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

16-Bit Microcontrollers with
Infrared Module and Optional USB
• Programmable 9th bit parity support
• Start/stop bit support
The dual-integrated SPI interfaces provide independent
serial communication channels that communicate syn-
chronously with peripheral devices in a multiple master
or multiple slave system. The interface allows access to
a 4-wire, full-duplex serial bus, and can be operated in
either master mode or slave mode. Collision detection
is provided when two or more masters attempt a data
transfer at the same time.
The maximum SPI master transfer rate is Sysclk/2. When
operating as an SPI slave, the MAXQ612/MAXQ622 can
support up to Sysclk/4 SPI transfer rate. Data is trans-
ferred as an 8-bit or 16-bit value, MSB first. In addition,
the SPI module supports configuration of an active SSEL
state through the slave active select. Separate pins and
registers are used to differentiate between the two SPI ports.
The microcontroller integrates an internal I
ter/slave for communication with a wide variety of other
I
rectional bus using two bus lines—the serial data line
(SDA) and the serial clock line (SCL)—and a ground line.
Both the SDA and SDL lines must be driven as open-
collector/drain outputs. External resistors are required as
shown in Figure 1 to pull the lines to a logic-high state.
The device supports both the master and slave proto-
cols. In the master mode, the device has ownership of
the I
and STOP signals. This allows it to send data to a slave
or receive data from a slave as required. In slave mode,
the device relies on an externally generated clock to
drive SCL and responds to data and commands only
when requested by the I
The integrated USB controller is compliant with the USB
2.0 specification, providing full-speed operation with the
newest generation of USB peripherals. The USB con-
troller functions as a full-speed USB peripheral device.
Integrating the USB physical interface (PHY) allows
direct connection to the USB cable, reducing board
space and overall system cost. A system interrupt can
be enabled to signal that the USB needs to be serviced.
The CPU communicates to the USB controller module
through the SFR interface. The microcontroller is seen
22
2
C–enabled peripherals. The I
2
_____________________________________________________________________________________
C bus, drives the clock, and generates the START
USB Controller (MAXQ622 Only)
Serial Peripheral Interface (SPI)
2
C master device.
2
C bus is a 2-wire, bidi-
2
C bus mas-
I
2
C Bus
by a USB host as a peripheral, characterized by the fol-
lowing endpoints:
• EP0: Bidirectional CONTROL endpoint with a 64-byte
• EP1-OUT: BULK (or INT) OUT endpoint. Double-
• EP2-IN: BULK (or INT) IN endpoint. Double-buffered
• EP3-IN: BULK (or INT) IN endpoint. Single-buffered 64
The choice to use EP1, EP2, and EP3 as BULK or
INTERRUPT endpoints is strictly a function of the end-
point descriptors that the USB controller returns to the
USB host during enumeration.
The USB controller communicates to a total of 384
bytes of endpoint data memory (2 x 64 bytes for each
data moving endpoint EP1 and EP2), 64 bytes for the
CONTROL endpoint, and 64 bytes for endpoint EP3.
Double-buffering EP1 and EP2 improves throughput by
allowing the CPU to read or load the next packet while
the USB controller is moving the current packet over
USB. EP3-IN is intended to serve as a large interrupt
endpoint for various USB class specifications such as
the Still Image Capture Device. It can also be used as a
second
An external quartz crystal or a ceramic resonator can be
connected between HFXIN and HFXOUT, as illustrated
in Figure 3.
To operate the core from an external clock, connect the
clock source to the HFXIN pin and connect the HFXOUT
Figure 3. On-Chip Oscillator
data storage.
buffered 64 bytes data storage.
64 bytes data storage.
bytes data storage.
C1
BULK IN endpoint.
C2
HFXOUT
HFXIN
V
DD
On-Chip Oscillator
R
F
R
C1 = C2 = 12pF
F
= 1MI Q50%
CLOCK CIRCUIT
STOP