UPD78F9222MC-5A4-A Renesas Electronics America, UPD78F9222MC-5A4-A Datasheet - Page 393

• Manufacturer Part Number: UPD78F9222MC-5A4-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222MC-5A4-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit timer/
event
counter
00
8-bit timer
80
Function
Capture
operation
Changing
compare
register during
timer operation
External event
counter
External clock
limitation
CR80: compare
register 80
TMC80: 8-bit
timer mode
control register
80
Interval timer
Error when
timer start
CR80: compare
register 80
Setting STOP
mode
Details of
Function
When the CRC001 bit value is 1, capture is not performed in the CR000 register
if both the rising and falling edges have been selected as the valid edges of the
TI000 pin.
When the CRC001 bit value is 1, the TM00 count value is not captured in the
CR000 register when a valid edge of the TI010 pin is detected, but the input
from the TI010 pin can be used as an external interrupt source because
INTTM000 is generated at that timing.
With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare
register, when changing CR0n0 around the timing of a match between 16-bit
timer counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0)
during timer counting, the change timing may conflict with the timing of the
match, so the operation is not guaranteed in such cases. To change CR0n0
during timer counting, INTTM000 interrupt servicing performs the following
operation.
If CR010 is changed during timer counting without performing processing <1>
above, the value in CR010 may be rewritten twice or more, causing an inversion
of the output level of the TO00 pin at each rewrite.
The timing of the count start is after two valid edge detections.
<1> When using an input pulse of the TI000 pin as a count clock (external
<2> When an external waveform is input to 16-bit timer/event counter 00, it is
When changing the value of CR80, be sure to stop the timer operation. If the
value of CR80 is changed with the timer operation enabled, a match interrupt
request signal is generated immediately and the timer may be cleared.
Be sure to set TMC80 after stopping the timer operation.
Be sure to clear bits 0 and 6 to 0.
When changing the value of CR80, be sure to stop the timer operation. If the
value of CR80 is changed with the timer operation enabled, a match interrupt
request signal may be generated immediately.
If the count clock of TMC80 is set and the operation of TM80 is enabled at the
same time by using an 8-bit memory manipulation instruction, the error of one
cycle after the timer is started may be 1 clock or more (refer to 7.5 (1) Error
when timer starts). Therefore, be sure to follow the above sequence when
using TM80 as an interval timer.
The time from starting the timer to generation of the match signal includes an
error of up to 1.5 clocks. This is because, if the timer is started while the count
clock is high, the rising edge may be immediately detected and the counter may
be incremented (refer to Figure 7-6).
8-bit compare register 80 (CR80) can be set to 00H.
Before executing the STOP instruction, be sure to stop the timer operation
(TCE80 = 0).
trigger), be sure to input the pulse width which satisfies the AC
characteristics. For the AC characteristics, refer to CHAPTER 21 and
CHAPTER 22 ELECTRICAL SPECIFICATIONS.
sampled by the noise limiter circuit and thus an error occurs on the timing
to become valid inside the device.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16898EJ6V0UD
Cautions
p. 124
p. 124
p. 125
p. 125
p. 126
p. 127
p. 130
p. 131
p. 131
p. 132
p. 132
p. 134
p. 134
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