SC5554MVR132 Freescale Semiconductor, SC5554MVR132 Datasheet - Page 10

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SC5554MVR132

Manufacturer Part Number
SC5554MVR132
Description
MCU MPC5554 DP ONLY 416-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC55xx Qorivvar
Datasheet

Specifications of SC5554MVR132

Core Processor
e200z6
Core Size
32-Bit
Speed
132MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
256
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.65 V
Data Converters
A/D 40x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC5554MVR132
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Electrical Characteristics
3.7
Power sequencing between the 1.5 V power supply and V
if using an external 1.5 V power supply with V
V
controller is not used. Refer to
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”
Power sequencing requires that V
before the POR signal negates. Refer to
VDD33.”
Although power sequencing is not required between V
not lead V
within specification. Higher spikes in the emitter current of the pass transistor occur if V
V
supply circuitry and the amount of board level capacitance.
1
2
3
4
5
6
7
8
9
10
11
10
Spec
RC33
DDSYN
The internal POR signals are V
RESET must remain asserted until the power supplies are within the operating conditions as specified in
Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the
internal POR asserts.
V
Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
At peak current for device.
Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the V
transistor to the V
(less than 1 Ω). V
bulk capacitor (greater than 4 μF over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01 μF, two 0.1 μF, and one 1 μF capacitors around the package on the V
Only available on devices that support -55
I
Refer to
Values are based on I
BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I
10
VRCCTL
8
9
IL_S
(Table
must be powered up within the specified operating range, even if the on-chip voltage regulator
Voltage differential during power up such that:
V
V
Absolute value of slew rate on power supply pins
Required gain at Tj:
I
DD
DD33
POR33
by more than these amounts. The value of that higher spike in current depends on the board power
is measured at the following conditions: V
Table 1
Power-Up/Down Sequencing
DDSYN
÷
I
9, Spec15) is guaranteed to scale with V
VRCCTL
can lag V
and V
for the maximum operating frequency.
RCCTL
DD
by more than 600 mV or lag by more than 100 mV for the V
POR5
(@ f
package signals must have a maximum of 100 nH inductance and minimal resistance
DD
DDSYN
must have a nominal 1 μF phase compensation capacitor to ground. V
RCCTL
sys
from high-use applications as explained in the I
Table 6. V
minimums respectively.
= f
or V
MAX
package signal to the base of the external pass transistor and between the emitter of the pass
POR15
DDEH6
)
Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),”
6, 8, 9, 10
Characteristic
MPC5554 Microcontroller Data Sheet, Rev. 3.0
, V
RC
DD33
POR33
before V
and POR Electrical Specifications (continued)
o
C.
must reach a certain voltage where the values are read as ones
– 55
– 40
25
150
, and V
Section 3.7.1, “Input Value of Pins During POR Dependent on
o
o
DDSYN
C
o
o
DD
C
C
C
7
POR5
DDEH6
= 1.35 V, V
RC33
and V
. On power up, assert RESET before the internal POR negates.
down to V
tied to ground (GND). To avoid power-sequencing,
DDEH6
RC33
RC33
DDSYN
reach the
= 3.1 V, V
and V
POR5
DD
.
or the RESET power supplies is required
Electrical Specification.
DDSYN
VRCCTL
DD
supply signals.
V
Symbol
DD33_LAG
BETA
during power up, V
= 2.2 V.
11
RC
DD
stage turn-on to operate
must have a 20 μF (nominal)
Freescale Semiconductor
105
Min.
85
70
70
RC33
11
Table 9
11
and
DD
leads or lags
Max.
÷
500
RC33
1.0
50
DC Electrical
I
VRCCTL
must
Units
V/ms
V
).

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