DF2168VTE33 Renesas Electronics America, DF2168VTE33 Datasheet - Page 499
![MCU FLASH 3V 256K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2168VTE33
Manufacturer Part Number
DF2168VTE33
Description
MCU FLASH 3V 256K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2168VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2168VTE33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 499 of 876
- Download datasheet (5Mb)
Bit
2
1
Bit Name
AAS
ADZ
Initial
Value
0
0
R/W
R/(W)* Slave Address Recognition Flag
R/(W)* General Call Address Recognition Flag
Description
In I
the first frame following a start condition matches bits
SVA6 to SVA0 in SAR, or if the general call address (H'00)
is detected.
[Setting condition]
When the slave address or general call address (one
frame including a R/W bit is H'00) is detected in slave
receive mode and FS = 0 in SAR
[Clearing conditions]
•
•
•
In I
the first frame following a start condition is the general call
address (H'00).
[Setting condition]
When the general call address (one frame including a R/W
bit is H'00) is detected in slave receive mode and FS = 0
or FSX = 0
[Clearing conditions]
•
•
•
If a general call address is detected while FS=1 and
FSX=0, the ADZ flag is set to 1; however, the general call
address is not recognized (AAS flag is not set to 1).
2
2
When ICDR is written to (transmit mode) or read from
(receive mode)
When 0 is written in AAS after reading AAS = 1
In master mode
When ICDR is written to (transmit mode) or read from
(receive mode)
When 0 is written in ADZ after reading ADZ = 1
In master mode
C bus format slave receive mode, this flag is set to 1 if
C bus format slave receive mode, this flag is set to 1 if
Rev. 3.00, 03/04, page 457 of 830
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