DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 318
DF2239TF16I
Manufacturer Part Number
DF2239TF16I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2239TF16I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2239TF16I
HD64F2239TF16I
HD64F2239TF16I
- Current page: 318 of 1048
- Download datasheet (6Mb)
Section 8 DMA Controller (DMAC)
8.5.8
An example of the basic DMAC bus cycle timing is shown in figure 8.18. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller
settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
Rev. 6.00 Mar. 18, 2010 Page 256 of 982
REJ09B0054-0600
Basic Bus Cycles
Address bus
CPU cycle
HWR
LWR
Figure 8.18 Example of DMA Transfer Bus Timing
RD
φ
T
1
address
Source
T
2
DMAC cycle (1-word transfer)
T
1
T
2
Destination address
T
3
T
1
T
2
T
3
CPU cycle
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