DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 257
DF2239TF16I
Manufacturer Part Number
DF2239TF16I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2239TF16I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2239TF16I
HD64F2239TF16I
HD64F2239TF16I
- Current page: 257 of 1048
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(2) Write after Read
(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Address bus
CS (area A)
CS (area B)
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an
idle cycle is inserted at the start of the write cycle.
Figure 7.22 shows an example of the operation in this case. In this example, bus cycle A is a
read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data
from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is
prevented.
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 7.23.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and
CS signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Data bus
HWR
RD
φ
(a) Idle cycle not inserted
(ICIS0 = 0)
T
1
Bus cycle A
Long output floating time
T
Figure 7.22 Example of Idle Cycle Operation (2)
2
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
Rev. 6.00 Mar. 18, 2010 Page 195 of 982
HWR
RD
φ
T
1
Bus cycle A
(b) Idle cycle inserted
(Initial value ICIS0 = 1)
T
Section 7 Bus Controller
2
T
3
REJ09B0054-0600
T
Bus cycle B
I
T
1
T
2
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