DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 290
DF2239TF16I
Manufacturer Part Number
DF2239TF16I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2239TF16I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2239TF16I
HD64F2239TF16I
HD64F2239TF16I
- Current page: 290 of 1048
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Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 228 of 982
REJ09B0054-0600
Bit
2
1
0
Bit Name
DTIE1A
DTIE0B
DTIE0A
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. If the DTE1 bit is
cleared to 1 when DTIE1A = 1, the DMAC
regards this as indicating the end of a transfer,
and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
0: Data transfer is disabled
1: Data transfer is enabled
Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted.
If the DTME0 bit is cleared to 0 when DTIE0B =
1, the DMAC regards this as indicating a break
in the transfer, and issues a transfer break
interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled
either by clearing the DTIE0B bit to 0 in the
interrupt handling routine, or by performing
processing to continue transfer by setting the
DTME0 bit to 1.
0: Data transfer is disabled
1: Data transfer is enabled
Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. If the DTE0 bit is
cleared to 0 when DTIE0A = 1, the DMAC
regards this as indicating the end of a transfer,
and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.
0: Data transfer is disabled
1: Data transfer is enabled
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