C8051F121-GQR Silicon Laboratories Inc, C8051F121-GQR Datasheet - Page 206
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C8051F121-GQR
Manufacturer Part Number
C8051F121-GQR
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F130/1/2/3
The Flash Access Limit security feature (see SFR Definition 15.1) protects proprietary program code and
data from being read by software running on the device. This feature provides support for OEMs that wish
to program the MCU with proprietary value-added firmware before distribution. The value-added firmware
can be protected while allowing additional code to be programmed in remaining program memory space
later.
The Flash Access Limit (FAL) is a 17-bit address that establishes two logical partitions in the program
memory space. The first is an upper partition consisting of all the program memory locations at or above
the FAL address, and the second is a lower partition consisting of all the program memory locations start-
ing at 0x00000 up to (but excluding) the FAL address. Software in the upper partition can execute code in
the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruc-
tion. (Executing a MOVC instruction from the upper partition with a source address in the lower partition
will return indeterminate data.) Software running in the lower partition can access locations in both the
upper and lower partition without restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-
added firmware via the reset vector. Once the value-added firmware completes its initial execution, it
branches to a predetermined location in the upper partition. If entry points are published, software running
in the upper partition may execute program code in the lower partition, but it cannot read or change the
contents of the lower partition. Parameters may be passed to the program code running in the lower parti-
tion either through the typical method of placing them on the stack or in registers before the call or by plac-
ing them in prescribed memory locations in the upper partition.
The FAL address is specified using the contents of the Flash Access Limit Register. The 8 MSBs of the 17-
bit FAL address are determined by the setting of the FLACL register. Thus, the FAL can be located on 512-
byte boundaries anywhere in program memory space. However, the 1024-byte erase sector size essen-
tially requires that a 1024 boundary be used. The contents of a non-initialized FLACL security byte are
0x00, thereby setting the FAL address to 0x00000 and allowing read access to all locations in program
memory space by default.
206
Bits 7–0: FLACL: Flash Access Limit.
R/W
Bit7
This register holds the most significant 8 bits of the 17-bit program memory read/write/erase
limit address. The lower 9 bits of the read/write/erase limit are always set to 0. A write to this
register sets the Flash Access Limit. This register can only be written once after any reset.
Any subsequent writes are ignored until the next reset. To fully protect all addresses
below this limit, bit 0 of FLACL should be set to ‘0’ to align the FAL on a 1024-byte
Flash page boundary.
R/W
Bit6
SFR Definition 15.1. FLACL: Flash Access Limit
R/W
Bit5
R/W
Bit4
Rev. 1.4
R/W
Bit3
R/W
Bit2
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
0xB7
F
SFR Address:
00000000
Reset Value
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