MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 34

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

SPACE —Address Space
IPL —Interrupt Priority Level
AVEC —Autovector Enable
3.5.5 Port C Data Register
PORTC — Port C Data Register
34
RESET:
15
Use this option field to select an address space for the chip-select logic. The CPU32 normally operates
in supervisor or user space, but interrupt acknowledge cycles must take place in CPU space.
If the space field is set for CPU space (00), chip-select logic can be used for interrupt acknowledge.
During an interrupt acknowledge cycle, the priority level on address lines ADDR[3:1] is compared to the
value in the IPL field. If the values are the same, a chip select is asserted, provided that other option
register conditions are met. The following table shows IPL field encoding.
This field only affects the response of chip selects and does not affect interrupt recognition by the CPU.
Any level means that chip select is asserted regardless of the level of the interrupt acknowledge cycle.
This field selects one of two methods of acquiring the interrupt vector during the interrupt acknowledge
cycle. It is not usually used in conjunction with a chip-select pin.
If the chip select is configured to trigger on an interrupt acknowledge cycle (SPACE = 00) and the AVEC
field is set to one, the chip select automatically generates an AVEC in response to the interrupt cycle.
Otherwise, the vector must be supplied by the requesting device.
The AVEC bit must not be used in synchronous mode, as autovector response timing can vary because
of ECLK synchronization.
Bit values in port C determine the state of chip-select pins used for discrete output. When a pin is as-
signed as a discrete output, the value in this register appears at the output. This is a read/write register.
Bit 7 is not used. Writing to this bit has no effect, and it always returns zero when read.
0 = External interrupt vector enabled
1 = Autovector enabled
NOT USED
Freescale Semiconductor, Inc.
For More Information On This Product,
Space Field
00
01
10
11
000
001
010
011
100
101
110
111
IPL
Go to: www.freescale.com
8
Supervisor/User Space
Supervisor Space
Description
Address Space
Any Level
CPU Space
User Space
7
0
0
IPL1
IPL2
IPL3
IPL4
IPL5
IPL6
IPL7
PC6
6
1
PC5
5
1
PC4
4
1
PC3
3
1
PC2
2
1
MC68331TS/D
PC1
$YFFA41
1
1
PC0
0
1