MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 22

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3.3.1 Clock Sources
22
22 pF
1. MUST BE LOW-LEAKAGE CAPACITOR (INSULATION RESISTANCE 30,000 M OR GREATER).
2. RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-kHz CRYSTAL.
V
SSI
The state of the clock mode (MODCLK) pin during reset determines the clock source. When MODCLK
is held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator
or an external reference input. Clock synthesizer control register SYNCR determines operating frequen-
cy and various modes of operation. When MODCLK is held low during reset, the clock synthesizer is
disabled, and an external system clock signal must be applied. When the synthesizer is disabled, SYN-
CR control bits have no effect.
A reference crystal must be connected between the EXTAL and XTAL pins to use the internal oscillator.
Use of a 32.768-kHz crystal is recommended. These crystals are inexpensive and readily available. If
an external reference signal or an external system clock signal is applied through the EXTAL pin, the
XTAL pin must be left floating. External reference signal frequency must be less than or equal to max-
imum specified reference frequency. External system clock signal frequency must be less than or equal
to maximum specified system clock frequency.
When an external system clock signal is applied (i.e., the PLL is not used), duty cycle of the input is
critical, especially at near maximum operating frequencies. The relationship between clock signal duty
cycle and clock signal period is expressed:
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
EXTAL
2
OSCILLATOR
32.768 KHz
CRYSTAL
10M
R3
330K
R4
XTAL
50% — percentage variation of external clock input duty cycle
22 pF
V
SSI
Freescale Semiconductor, Inc.
2
COMPARATOR
For More Information On This Product,
PHASE
Figure 7 System Clock Block Diagram
minimum external clock high/low time
Minimum external clock period =
Go to: www.freescale.com
SYSTEM CLOCK CONTROL
FEEDBACK DIVIDER
XFC PIN
LOW-PASS
FILTER
XFC
1
0.1 F
V DDSYN
V DDSYN
W
Y
X
0.01 F
0.1 F
VCO
V
SSI
SYSTEM
CLOCK
MC68331TS/D
CLKOUT
BLOCK 32KHZ
SYS CLOCK