MCF5214CVF66J Freescale Semiconductor, MCF5214CVF66J Datasheet - Page 614

• Manufacturer Part Number: MCF5214CVF66J
• Description: IC MCU 256K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF521x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52210DEMO, M52211EVB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Reset Controller Module
Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does
not wait for the current bus cycle to complete. Reset is asserted immediately to the system.
29.5.1.1 Power-On Reset
At power up, the reset controller asserts RSTO. RSTO continues to be asserted until V
has reached a
DD
minimum acceptable level and, if PLL clock mode is selected, until the PLL achieves phase lock. Then
after approximately another 512 cycles, RSTO is negated and the part begins operation.
29.5.1.2 External Reset
Asserting the external RSTI for at least four rising CLKOUT edges causes the external reset request to be
recognized and latched. The bus monitor is enabled and the current bus cycle is completed. The reset
controller asserts RSTO for approximately 512 cycles after RSTI is negated and the PLL has acquired lock.
The part then exits reset and begins operation.
In low-power stop mode, the system clocks are stopped. Asserting the external RSTI in stop mode causes
an external reset to be recognized.
29.5.1.3 Watchdog Timer Reset
A watchdog timer timeout causes timer reset request to be recognized and latched. The bus monitor is
enabled and the current bus cycle is completed. If the RSTI is negated and the PLL has acquired lock, the
reset controller asserts RSTO for approximately 512 cycles. Then the part exits reset and begins operation.
29.5.1.4 Loss-of-Clock Reset
This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set and either the
PLL reference or the PLL itself fails. The reset controller asserts RSTO for approximately 512 cycles after
the PLL has acquired lock. The part then exits reset and begins operation.
29.5.1.5 Loss-of-Lock Reset
This reset condition occurs in PLL clock mode when the LOLRE bit in the SYNCR is set and the PLL
loses lock. The reset controller asserts RSTO for approximately 512 cycles after the PLL has acquired
lock. The part then exits reset and resumes operation.
29.5.1.6 Software Reset
A software reset occurs when the SOFTRST bit is set. If the RSTI is negated and the PLL has acquired
lock, the reset controller asserts RSTO for approximately 512 cycles. Then the part exits reset and resumes
operation.
29.5.1.7 LVD Reset
The LVD reset will occur when the supply input voltage, V
drops below V
(minimum).
DD,
LVD
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
29-6
Freescale Semiconductor