MCF5214CVF66J Freescale Semiconductor, MCF5214CVF66J Datasheet - Page 138

• Manufacturer Part Number: MCF5214CVF66J
• Description: IC MCU 256K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF521x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52210DEMO, M52211EVB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Power Management
7.2.2
7.2.3
The following subsection describes the PMM registers.
7.2.3.1
Implementation of low-power stop mode and exit from a low-power mode via an interrupt require
communication between the CPU and logic associated with the interrupt controller. The LPICR is an 8-bit
register that enables entry into low-power stop mode, and includes the setting of the interrupt level needed
to exit a low-power mode.
Following is the sequence of operations needed to enable this functionality:
7-2
1
2
3
1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired low-power
2. At the appropriate time, the processor executes the privileged STOP instruction. Once the
3. The entry into a low-power mode is processed by the low-power mode control logic, and the
4. After entering the low-power mode, the interrupt controller enables a combinational logic path
IPSBAR Offset
S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in
a cycle termination transfer error.
The CRSR, CWCR, and CWSR are described in the System Integration Module. They are shown here only to warn
against accidental writes to these registers when accessing the LPICR.
The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to this
register when accessing the LPCR.
0x0000_0010
0x0011_0004
mode) and loading the appropriate interrupt priority level.
processor has stopped execution, it asserts a specific Processor Status (PST) encoding. Issuing the
STOP instruction when the LPICR[ENBSTOP] bit is set causes the SCM to enter stop mode.
appropriate clocks (usually those related to the high-speed processor core) are disabled.
which evaluates any unmasked interrupt requests. The device waits for an event to generate an
interrupt request with a priority level greater than the value programmed in
LPICR[XLPM_IPL[2:0]].
Memory Map
Register Descriptions
Low-Power Interrupt Control Register (LPICR)
The setting of the low-power mode select (LPMD) field in the power
management module’s low-power control register (LPCR) determines
which low-power mode the device enters when a STOP instruction is issued.
If this field is set to enter stop mode, then the ENBSTOP bit in the LPICR
must also be set.
Chip Configuration Register (CCR)
Core Reset Status
Register (CRSR)
Bits 31–24
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 7-1. Chip Configuration Module Memory Map
2
Control Register
Core Watchdog
Bits 23–16
(CWCR)
3
NOTE
Register (LPICR)
Interrupt Control
Low-Power
Bits 15–8
Reserved
Low-Power Control
Service Register
Register (LPCR)
Core Watchdog
Bits 7–0
(CWSR)
Freescale Semiconductor
Access
S
S
1