C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 211
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C8051F130-GQR
Manufacturer Part Number
C8051F130-GQR
Description
IC 8051 MCU 128K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F130-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F130-GQR
Manufacturer:
TI
Quantity:
679
Company:
Part Number:
C8051F130-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
16. Branch Target Cache
The C8051F12x and C8051F13x device families incorporate a 63x4 byte branch target cache with a 4-byte
prefetch engine. Because the access time of the Flash memory is 40 Flashns, and the minimum instruction
time is 10ns (C8051F120/1/2/3 and C8051F130/1/2/3) or 20 ns (C8051F124/5/6/7), the branch target
cache and prefetch engine are necessary for full-speed code execution. Instructions are read from Flash
memory four bytes at a time by the prefetch engine, and given to the CIP-51 processor core to execute.
When running linear code (code without any jumps or branches), the prefetch engine alone allows instruc-
tions to be executed at full speed. When a code branch occurs, a search is performed for the branch tar-
get (destination address) in the cache. If the branch target information is found in the cache (called a
“cache hit”), the instruction data is read from the cache and immediately returned to the CIP-51 with no
delay in code execution. If the branch target is not found in the cache (called a “cache miss”), the proces-
sor may be stalled for up to four clock cycles while the next set of four instructions is retrieved from Flash
memory. Each time a cache miss occurs, the requested instruction data is written to the cache if allowed
by the current cache settings. A data flow diagram of the interaction between the CIP-51 and the Branch
Target Cache and Prefetch Engine is shown in Figure 16.1.
Instruction
Data
CIP-51
FLASH
Memory
Prefetch
Branch Target
Engine
Cache
Instruction Address
Figure 16.1. Branch Target Cache Data Flow
16.1. Cache and Prefetch Operation
The branch target cache maintains two sets of memory locations: “slots” and “tags”. A slot is where the
cached instruction data from Flash is stored. Each slot holds four consecutive code bytes. A tag contains
the 15 most significant bits of the corresponding Flash address for each four-byte slot. Thus, instruction
data is always cached along four-byte boundaries in code space. A tag also contains a “valid bit”, which
indicates whether a cache location contains valid instruction data. A special cache location (called the lin-
ear tag and slot), is reserved for use by the prefetch engine. The cache organization is shown in
Figure 16.2. Each time a Flash read is requested, the address is compared with all valid cache tag loca-
tions (including the linear tag). If any of the tag locations match the requested address, the data from that
slot is immediately provided to the CIP-51. If the requested address matches a location that is currently
being read by the prefetch engine, the CIP-51 will be stalled until the read is complete. If a match is not
found, the current prefetch operation is abandoned, and a new prefetch operation is initiated for the
requested instruction data. When the prefetch operation is finished, the CIP-51 begins executing the
instructions that were retrieved, and the prefetch engine begins reading the next four-byte word from Flash
memory. If the newly-fetched data also meets the criteria necessary to be cached, it will be written to the
cache in the slot indicated by the current replacement algorithm.
Rev. 1.4
211
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