C8051F062-GQR Silicon Laboratories Inc, C8051F062-GQR Datasheet - Page 266

• Manufacturer Part Number: C8051F062-GQR
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F062-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 59
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 336-1214 - DEV KIT FOR F060/F062/F063
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C8051F060/1/2/3/4/5/6/7
22.1. UART0 Operational Modes
UART0 provides four operating modes (one synchronous and three asynchronous) selected by setting
configuration bits in the SCON0 register. These four modes offer different baud rates and communication
protocols. The four modes are summarized in Table 22.1.
22.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the
RX0 pin. The TX0 pin provides the shift clock for both transmit and receive. The MCU must be the master
since it generates the shift clock for transmission in both directions (see the interconnect diagram in
Figure 22.3).
Data transmission begins when an instruction writes a data byte to the SBUF0 register. Eight data bits are
transferred LSB first (see the timing diagram in Figure 22.2), and the TI0 Transmit Interrupt Flag
(SCON0.1) is set at the end of the eighth bit time. Data reception begins when the REN0 Receive Enable
bit (SCON0.4) is set to logic 1 and the RI0 Receive Interrupt Flag (SCON0.0) is cleared. One cycle after
the eighth bit is shifted in, the RI0 flag is set and reception stops until software clears the RI0 bit. An inter-
rupt will occur if enabled when either TI0 or RI0 are set.
266
Mode
0
1
2
3
Synchronization
Asynchronous
Asynchronous
Asynchronous
Synchronous
SYSCLK / 32 or SYSCLK / 64
Table 22.1. UART0 Modes
Timer 1, 2, 3, or 4 Overflow
Timer 1, 2, 3, or 4 Overflow
SYSCLK / 12
Baud Clock
Rev. 1.2
Data Bits
8
8
9
9
Start/Stop Bits
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
None