C8051F062-GQR Silicon Laboratories Inc, C8051F062-GQR Datasheet - Page 208

• Manufacturer Part Number: C8051F062-GQR
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F062-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 59
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 336-1214 - DEV KIT FOR F060/F062/F063
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C8051F060/1/2/3/4/5/6/7
18.1.6. Crossbar Pin Assignment Example
In this example (Figure 18.4), we configure the Crossbar to allocate Port pins for UART0, the SMBus, all 6
PCA modules, /INT0, and /INT1 (12 pins total). Additionally, we configure P1.2, P1.3, and P1.4 for Analog
Input mode so that the voltages at these pins can be measured by ADC2. The configuration steps are as
follows:
XBR0, XBR1, and XBR2 are set such that UART0EN = 1, SMB0EN = 1, PCA0ME = ‘110’, INT0E = 1, and
INT1E = 1. Thus: XBR0 = 0x3D, XBR1 = 0x14, and XBR2 = 0x40.
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1. We configure the desired Port 1 pins to Analog Input mode by setting P1MDIN to 0xE3 (P1.4,
2. We enable the Crossbar by setting XBARE = 1: XBR2 = 0x40.
3. We set the UART0 TX pin (TX0, P0.0) output and the CEX0-3 outputs to Push-Pull by setting
4. We explicitly disable the output drivers on the 3 Analog Input pins by setting the corresponding
P1.3, and P1.2 are Analog Inputs, so their associated P1MDIN bits are set to logic 0).
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P0MDOUT = 0xF1.
bits in the P1MDOUT register to ‘0’, and in P1 to ‘1’. Additionally, the CEX5-4 output pins are
set to Push-Pull mode. Therefore, P1MDOUT = 0x03 (configure unused pins to Open-Drain)
and P1 = 0xFF (a logic 1 selects the high-impedance state).
UART0 has the highest priority, so P0.0 is assigned to TX0, and P0.1 is assigned to RX0.
The SMBus is next in priority order, so P0.2 is assigned to SDA, and P0.3 is assigned to
SCL.
PCA0 is next in priority order, so P0.4 through P1.1 are assigned to CEX0 through CEX5
P1MDIN is set to 0xE3, which configures P1.2, P1.3, and P1.4 as Analog Inputs, causing
the Crossbar to skip these pins.
/INT0 is next in priority order, so it is assigned to the next non-skipped pin, which is P1.5.
/INT1 is next in priority order, so it is assigned to P1.6.
Rev. 1.2