DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 590

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 I
When, with the I
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag is not
set at the end of a data transfer up to detection of a retransmission start condition or stop condition
after a slave address (SVA) or general call address match in I
Tables 18.5 and 18.6 show the relationship between the flags and the transfer states.
Table 18.5 Flags and Transfer States (Master Mode)
MST
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 2.00 Sep. 28, 2009 Page 548 of 994
REJ09B0452-0200
TRS
1
1
—
1
1
1
1
1
1
0
0
0
0
0
2
BBSY ESTP STOP IRTR
0
1↑
1
1
1
1
1
1
1
1
1
1
1
1
C Bus Interface (IIC)
2
C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1↑
—
—
1↑
—
—
—
1↑
1↑
—
—
—
1↑
AASX AL
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AAS
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
ADZ
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
ACKB ICDRF ICDRE State
0
0
—
1↑
0
0
0
0
0
—
—
—
—
—
2
C bus format slave mode.
—
—
—
—
—
—
—
—
—
1↑
0↓
1
0↓
1↑
0
1↑
—
—
1↑
0↓
1
0↓
1↑
—
—
—
—
—
Idle state (flag clearing
required)
Start condition detected
Wait state
Transmission end
(ACKE=1 and ACKB=1)
Transmission end with
ICDRE=0
ICDR write with the
above state
Transmission end with
ICDRE=1
ICDR write with the
above state or after start
condition detected
Automatic data transfer
from ICDRT to ICDRS
with the above state
Reception end with
ICDRF=0
ICDR read with the
above state
Reception end with
ICDRF=1
ICDR read with the
above state
Automatic data transfer
from ICDRS to ICDRR
with the above state