DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 540

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3.3
FTSR is a register that converts parallel data from the FTxD pin to serial data and then transmits
the serial data. When one frame transmission of serial data is completed, the next data is
transferred from FTHR. The serial data is transmitted from the LSB (bit 0).
FTSR cannot be written from the H8S CPU/LPC interface.
17.3.4
FTHR is an 8-bit write-only register that stores serial transmit data. It is accessible when the
DLAB bit in FLCR is 0. Write transmit data while the THRE bit in FLCR is set to 1.
Data can be written to FTHR when the THRE bit is set with the FIFO disabled. If data is written to
FTHR when the THRE bit is not set, the data is overwritten.
While the THRE bit is set with the FIFO enabled, up to 16 bytes of data can be written. If data is
written with the FIFO full, the written data is lost.
17.3.5
The FDLH and FDLL are registers used to set the baud rate. They are accessible when the DLAB
bit in FLCR is 1. Frequency division ranging from 1 to (2
The frequency divider circuit stops when both of FDLH and FDLL are 0 (initial value).
• FDLH
Rev. 2.00 Sep. 28, 2009 Page 498 of 994
REJ09B0452-0200
Bit
7 to 0
Bit
7 to 0
Bit Name
Bit 7 to
bit 0
Bit Name
Bit 7 to
bit 0
Transmitter Shift Register (FTSR)
Transmitter Holding Register (FTHR)
Divisor Latch H, L (FDLH, FDLL)
Initial Value
⎯
Initial Value
All 0
R/W
W
R/W
R/W
Description
Stores serial data to be transmitted.
The data is 16 bytes when the FIFO is enabled.
Description
Upper 8 bits of divisor latch
16
− 1) can be set with these registers.