MCF5212CAE66 Freescale Semiconductor, MCF5212CAE66 Datasheet - Page 8
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MCF5212CAE66
Manufacturer Part Number
MCF5212CAE66
Description
IC MCU 256K FLASH 66MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5213CAF80.pdf
(54 pages)
Specifications of MCF5212CAE66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
MCF521x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, QSPI, UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
56
Number Of Timers
10
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Minimum Operating Temperature
0 C
On-chip Adc
12 bit, 8 Channel
For Use With
M5211DEMO - KIT DEMO FOR MCF5211
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5212CAE66
Manufacturer:
FREESCAL
Quantity:
1 210
Company:
Part Number:
MCF5212CAE66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5212CAE66
Manufacturer:
FREESCALE
Quantity:
20 000
Family Configurations
1.2.2
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage
instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is
a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).
The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with support for a separate user stack pointer
register and four new instructions to assist in bit processing. Additionally, the core includes the multiply-accumulate (MAC)
unit for improved signal processing capabilities. The MAC implements a three-stage arithmetic pipeline, optimized for 16x16
bit operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned
integers, signed fractional operands, and a complete set of instructions to process these data types. The MAC provides support
for execution of DSP operations within the context of a single processor at a minimal hardware cost.
1.2.3
The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator
development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided
on 100-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit
emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,
a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint
registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or
dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
This device implements revision B+ of the ColdFire Debug Architecture.
The processor’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be
serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports.
These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining
processor activity at the CPU’s clock rate. The device includes a new debug signal, ALLPST. This signal is the logical AND of
the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
8
•
•
•
— Status flag indication of source of last reset
Chip configuration module (CCM)
— System configuration during reset
— Selects one of six clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
General purpose I/O interface
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
– Loss of lock
– Low-voltage detection (LVD)
V2 Core Overview
Integrated Debug Module
MCF5213 ColdFire Microcontroller, Rev. 4
Freescale Semiconductor