MCF52233CAL60 Freescale Semiconductor, MCF52233CAL60 Datasheet - Page 26

• Manufacturer Part Number: MCF52233CAL60
• Description: IC MCU 256K FLASH 60MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF5223xr

Specifications of MCF52233CAL60

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 73
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Cpu Family: MCF5223x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 60MHz
• Interface Type: I2C/QSPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 10
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Processor Series: MCF522x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 10
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52235EVB, M52233DEMO
• Minimum Operating Temperature: - 40 C
• Package: 112LQFP
• Family Name: MCF5223x
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• For Use With: M52233DEMO - BOARD DEMO FOR MCF52233
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

MCF52235 Family Configurations
26
Processor Status Clock
All Processor Status
Development Serial
Development Serial
Development Serial
Test Data Output
Processor Status
Signal Name
Debug Data
Breakpoint
Outputs
Outputs
Output
Clock
Input
Abbreviation
DDATA[3:0]
PSTCLK
PST[3:0]
ALLPST
DSCLK
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
BKPT
TDO
DSO
DSI
Table 16. Debug Support Signals (continued)
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
Development Serial Clock. Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
Breakpoint. Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor status
signals (PST[3:0]) as the value 0xF. If CSR[BKD] is set (disabling
normal BKPT functionality), asserting BKPT generates a debug
interrupt exception in the processor.
Development Serial Input. Internally synchronized input that provides
data input for the serial communication port to the debug module after
the DSCLK has been seen as high (logic 1).
Development Serial Output. Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
Processor Status Clock. Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, PST,
and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be re-enabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
Logical AND of PST[3:0]
Function
Freescale Semiconductor
I/O
O
O
O
O
O
O
I
I
I