MCF5232CVM100J Freescale Semiconductor, MCF5232CVM100J Datasheet - Page 46
MCF5232CVM100J
Manufacturer Part Number
MCF5232CVM100J
Description
IC MCU 64K SRAM 100MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF523xr
Datasheet
1.MCF5232CVM100J.pdf
(48 pages)
Specifications of MCF5232CVM100J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
97
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF523x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5234-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5232CVM100J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Document Revision History
46
Rev. No.
1.5
1.6
1.7
1.8
2
3
4
• Removed Overview, Features, Modes of Operation, and Address Multiplexing sections. This
• Removed list of documentation table in
•
•
• Added
• Updated 196MAPBGA package dimensions,
•
•
• Removed second sentence from
• Removed third and fourth paragraphs from
•
•
•
• Corrected position of spec D5 in
•
•
• Added part number MCF5235CVF150 in
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
information can be found in the MCF5235 Reference Manual.
always available on our web site.
Table
Table
Table
QSPI_CS1 pin location from “—” to 139 for the 160QFP device.
Figure
ERXDV, ERXER, and
ETXEN, ETXER,
(ETXD[3:0], ETXEN, ETXER,
Section 5.2.1, “Supply Voltage Sequencing and Separation
V
Section 5.2.1, “Supply Voltage Sequencing and Separation
voltage level from 1.5V to 3.3V throughout section.
Section 5.2.1.1, “Power Up
Table
Table
DDPLL
Table 26. MCF5235EC Revision History (continued)
9: Changed core supply voltage (V
10: Changed max f
2: Changed SD_CKE pin location from 139 to “—” for the 160QFP device. Changed
14: Added DACKn and DREQn to footnote.
9, added PLL supply voltage row
Section 5.2.1, “Supply Voltage Sequencing and Separation
8: Changed pin 139 label from “SD_CKE/QSPI_CS1” to “QSPI_CS1/SD_CKE”.
to match rest of document.
ETXCLK),”
ERXCLK),”
ICO
Sequence” first bullet, changed “Use 1 µs” to “Use 1 ms”.
frequency from “75 MHz” to “150 MHz”.
regarding no minimum frequency requirement for TXCLK.
ETXCLK),”
Substantive Change(s)
Figure
and
Section 7.10.1, “MII Receive Signal Timing (ERXD[3:0],
Section 7.10.2, “MII Transmit Signal Timing (ETXD[3:0],
Section 8,
14.
DD
Table 6
as this feature is not supported on this device.
) from 1.35-1.65 to 1.4-1.6.
Section 7.10.2, “MII Transmit Signal Timing
Figure
“Documentation.”. An up-to-date list is
3.
Cautions” changed PLLV
Cautions” Changed V
Cautions.”
Freescale Semiconductor
DDPLL
DD
to