M38039FFLHP#U0 Renesas Electronics America, M38039FFLHP#U0 Datasheet - Page 45

• Manufacturer Part Number: M38039FFLHP#U0
• Description: IC 3803 MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039FFLHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.L)
Rev.1.01
REJ03B0212-0101
SERIAL INTERFACE
• Serial I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O. A dedicated timer is also
provided for baud rate generation.
Fig 36. Block diagram of clock synchronous serial I/O1
Fig 37. Operation of clock synchronous serial I/O1
Write pulse to receive/transmit
buffer register 1 (address 0018
P4
7
/S
Receive enable signal S
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
RDY1
P4
(f(X
P4
P4
/CNTR
6
4
5
/S
CIN
/R
/T
f(X
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Jan 25, 2008
CLK1
X
X
) in low-speed mode)
D
D
IN
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
continuously from the T
Serial output T
1
2
1
)
Serial input R
BRG count source selection bit
F/F
RDY1
X
X
D
D
16
1
1
)
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TBE = 0
X
1/4
D pin.
Falling-edge detector
TBE = 1
TSC = 0
Receive buffer register 1
Receive shift register 1
D
D
0
0
Serial I/O1 synchronous clock selection bit
Data bus
Transmit buffer register 1
Transmit shift register 1
Data bus
D
D
Address 0018
1
1
Shift clock
Frequency division ratio 1/(n+1)
Baud rate generator 1
Shift clock
Address 0018
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control
register (bit 6 of address 001A
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
D
D
2
2
16
Address 001C
16
Clock control circuit
D
D
Clock control circuit
3
3
Serial I/O1 control register
Transmit interrupt source selection bit
Receive buffer full flag (RBF)
Serial I/O1 status register
16
1/4
D
D
4
4
Receive interrupt request (RI)
16
D
D
Transmit buffer empty flag (TBE)
5
5
) to “1”.
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
D
D
6
6
Address 001A
Address 0019
Overrun error (OE)
detection
RBF = 1
TSC = 1
D
D
7
7
16
16