C8051F010-GQ Silicon Laboratories Inc, C8051F010-GQ Datasheet - Page 164
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C8051F010-GQ
Manufacturer Part Number
C8051F010-GQ
Description
IC 8051 MCU 32K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F01xr
Specifications of C8051F010-GQ
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1191
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F010-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
21. JTAG (IEEE 1149.1)
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing,
Flash read and write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the
IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-
Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Registers (DR) are as described in the
Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is via four dedicated pins on the MCU, which are TCK, TMS, TDI, and TDO. These pins are
all 5V tolerant.
Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 21.1 can be
commanded. There are three Data Registers (DR’s) associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
Bit15
IR value
0x0000
0x0002
0x0004
0xFFFF
0x0082
0x0083
0x0084
0x0085
Instruction
EXTEST
SAMPLE/
PRELOAD
IDCODE
BYPASS
Flash Control
Flash Data
Flash Address
Flash Scale
Figure 21.1. IR: JTAG Instruction Register
Description
Selects the Boundary Data Register for control and observability of all
device pins
Selects the Boundary Data Register for observability and presetting the
scan-path latches
Selects device ID Register
Selects Bypass Data Register
Selects FLASHCON Register to control how the interface logic responds to
reads and writes to the FLASHDAT Register
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects FLASHADR Register which holds the address of all Flash read,
write, and erase operations
Selects FLASHSCL Register which controls the prescaler used to generate
timing signals for Flash operations
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Bit0
Reset Value
0x0004
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