R5F363AENFA#U0 Renesas Electronics America, R5F363AENFA#U0 Datasheet - Page 100

• Manufacturer Part Number: R5F363AENFA#U0
• Description: MCU 4KB FLASH 256/16K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C/60/63r

Specifications of R5F363AENFA#U0

• Core Processor: M16C/60
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SIO, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/63 Group
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 98 of 113
Switching Characteristics
(V
Table 5.58
Notes:
CC1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
h(WR-CS)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
d(DB-WR)
h(WR-DB)
d(BCLK-HLDA)
d(BCLK-ALE)
h(BCLK-ALE)
d(AD-ALE)
h(AD-ALE)
d(AD-RD)
d(AD-WR)
dz(RD-AD)
5.3.4.3
1.
2.
3.
4.
5.
= V
Symbol
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
When using multiplexed bus, set f
0.5 10
--------------------- - 10 ns
(
----------------------------------- - 50 ns
0.5 10
--------------------- - 40 ns
0.5 10
--------------------- - 15 ns
CC2
f
f
f
n 0.5
(
(
(
BCLK
BCLK
BCLK
–
f
×
×
×
(
BCLK
= 3 V, V
)
)
)
) 10
9
9
9
In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus)
×
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
HLDA
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of address
WR signal output delay from the end of address
Address output floating start time
–
–
–
)
9
[
[
[
SS
–
output delay time
]
]
]
= 0 V, at T
[
]
n is 2 for 2 waits setting, 3 for 3 waits setting.
opr
(BCLK)
= -20 to 85 ° C/-40 to 85 ° C unless otherwise specified)
Parameter
12.5 MHz or less.
Figure 5.28
Measuring
Condition
See
(5)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 1)
(Note 3)
(Note 4)
Min.
5. Electrical Characteristics
− 4
0
0
0
0
0
0
0
Standard
V
CC1
Max.
= V
50
50
40
40
50
40
25
8
CC2
= 3 V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns