MC56F8322VFAE Freescale Semiconductor, MC56F8322VFAE Datasheet
MC56F8322VFAE
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MC56F8322VFAE Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8322 Rev. 16 04/2007 freescale.com ...
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... Corrected typo in ; added note on V and REFH Table 4-12; Table 10-14; and new graphs in Figure 10-20. Table 10-1. Table 10-7 and clarified Section 12.3. Table 10-1; also removed overall Table 13-1. Table 2-2. Clarified external reference Freescale Semiconductor Preliminary ...
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... Added the following note to the description of the TMS signal in Note: Rev. 16 Changed the “Frequency Accuracy” specification in Please see http://www.freescale.com for the most current data sheet revision. Freescale Semiconductor Preliminary Description of Change Always tie the TMS pin to V through a 2.2K resistor. ...
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... Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... SCI0 or GPIOC Decoding Peripherals FlexCAN or 2 GPIOC Freescale Semiconductor Preliminary • FlexCAN module • two Serial Communication Interfaces (SCIs) • two Serial Peripheral Interfaces (SPIs) • Two general-purpose Quad Timers • Computer Operating Properly (COP)/Watchdog • On-Chip Relaxation Oscillator • ...
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... Thermal Design Considerations . . . . . . . 131 12.2. Electrical Design Considerations . . . . . . .132 12.3. Power Distribution and I/O Ring Part 13: Ordering Information . . . . . . . . . 134 56F8322 Techncial Data, Rev. 16 and Interrupt Timing . . . . . . . . . . 113 (SCI) Timing . . . . . . . . . . . . . . . . .119 (ADC) Parameters . . . . . . . . . . . .121 Pin-Out Information . . . . . . . . . . .126 Information . . . . . . . . . . . . . . . . . 128 Implementation . . . . . . . . . . . . . .133 Freescale Semiconductor Preliminary ...
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... Differences Between Devices Table 1-1 outlines the key differences between the 56F8322 and 56F8122 devices. Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quadrature Decoder Temperature Sensor Dedicated GPIO Freescale Semiconductor Preliminary Table 1-1 Device Differences 56F8322 60MHz/60 MIPS 4KB 8KB — ...
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... General Purpose I/O (GPIO) pins • Integrated Power-On Reset and Low-Voltage Interrupt Module • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging • Software-programmable, Phase Lock Loop (PLL) • On-chip relaxation oscillator 8 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value Freescale Semiconductor Preliminary 56F8322 Technical Data, Rev. 16 ...
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... A complete set of evaluation modules (EVMs), demonstration board kit and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 10 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... C, Channel 2, input as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. Freescale Semiconductor Preliminary Figure 1-1 and ...
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... The primary data RAM port is 32 bits wide. Other data ports are 12 pab[20:0] cdbw[31:0] xab1[23:0] xab2[23:0] Figure 1-1 System Bus Interfaces 56F8322 Techncial Data, Rev. 16 Boot Flash Program Flash Program RAM Data RAM Data Flash To Flash Control Logic IPBus Bridge Flash Memory Module IPBus 16 bits. Freescale Semiconductor Preliminary ...
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... CLKGEN (OSC/PLL) (ROSC) Timer A 4 Quadrature Decoder 0 2 FlexCAN 4 2 Not available on the 56F8122 device. Freescale Semiconductor Preliminary To/From IPBus Bridge SCI 1 SPI 0 GPIO A GPIO B GPIO C IPBus Figure 1-2 Peripheral Subsystem 56F8322 Technical Data, Rev. 16 Architecture Block Diagram Interrupt Controller Low-Voltage Interrupt POR & ...
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... Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced Table 1-2 Bus Signal Names Function Program Memory Interface Primary Data Memory Interface Bus 1 , words, and long data types. Data is written Secondary Data Memory Interface Peripheral Interface Bus 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... Product Documentation The documents listed in Table 1-3 and 56F8122 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com/semiconductors/. Topic DSP56800E Detailed description of the 56800E family architecture, Reference Manual 16-bit controller core processor, and the instruction set ...
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... Pins can function as SCI #0 and GPIO. 6. Tied internally to ANA7 Note: See Table 1-1 for 56F8122 functional differences. 16 Figure 2-1 and Figure Number of Pins in Package 56F8322 — — 56F8322 Techncial Data, Rev. 16 2-2. In Table 2-2, each table row 56F8122 — 8 — — — 5 Freescale Semiconductor Preliminary ...
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... SSA_ADC Ground Other CAP Supply Ports EXTAL (GPIOC0) PLL and Clock or XTAL (GPIOC1) GPIO JTAG/ EOnCE Port Figure 2-1 56F8322 Signals Identified by Functional Group (48-Pin LQFP) Note tied to V and V REFH DDA REFLO Freescale Semiconductor Preliminary V 1 DD_IO 56F8322 1 2 CAP ...
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... GPIO SS0 (TXD1, GPIOB0) GPIOA0 - 1 SS1 (GPIOA2) MISO1 (GPIOA3) SPI1 or GPIO MOSI1 (GPIOA4) SCLK1 (GPIOA5) GPIOA6 ANA0 - 2 ANA4 - 6 ADCA V REF GPIOC2 GPIO GPIOC3 Quad Timer C TC0 (TXD0, GPIOC6) or SCI0 or TC1 (RXD0, GPIOC5) GPIO IRQA (V ) Interrupt/ PP Program RESET Control Freescale Semiconductor Preliminary ...
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... Supply CAP CAP Freescale Semiconductor Preliminary Table 2-2. Any alternate functionality must be programmed. State During Reset I/O Power — This pin supplies 3.3V power to the chip I/O interface and also the Processor core throught the on-chip voltage regulator enabled. ADC Power — This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. Ground — ...
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... Test Data Output — This tri-stateable output pin provides a serial output is output data stream from the JTAG/EOnCE port driven in the disabled, shift-IR and shift-DR controller states, and changes on the falling edge pull- TCK. enabled 56F8322 Techncial Data, Rev. 16 Signal Description . through a 2.2K resistor. DD Freescale Semiconductor Preliminary ...
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... Schmitt Input/ Output (GPIOB6) Schmitt Input/ Output (SYS_CLK2) Output Freescale Semiconductor Preliminary State During Reset Input, Phase A — Quadrature Decoder 0, PHASEA input pull-up enabled TA0 — Timer A, Channel 0 Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ...
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... A Schmitt trigger input is used for noise immunity. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCLK0. 56F8322 Techncial Data, Rev. 16 Signal Description CLKO Select Register, SIM_CLKOSR). Freescale Semiconductor Preliminary ...
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... Output PWMA0 3 Schmitt Output (GPIOA0) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Reset In reset, SPI 0 Master Out/Slave In — This serial data pin is an output from a output is master device and an input to a slave device. The master device disabled, places data on the MOSI line a half-cycle before the clock edge the pull-up is slave device uses to latch the data ...
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... Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8322, the default state after reset is PWMA3. In the 56F8122, the default state is not one of the functions offered and must be reconfigured. 56F8322 Techncial Data, Rev. 16 Signal Description Freescale Semiconductor Preliminary ...
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... ANA2 22 ANA4 23 Input ANA5 24 ANA6 25 Freescale Semiconductor Preliminary State During Reset In reset, PWMA4 — This is one of six PWMA output pins. output is disabled, SPI 1 Master Out/Slave In — This serial data pin is an output from a pull-up is master device and an input to a slave device. The master device ...
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... Transmit Data — SCI0 transmit data output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TC0. 56F8322 Techncial Data, Rev. 16 Signal Description — Internal pins for voltage reference which Freescale Semiconductor Preliminary ...
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... IRQA 11 Schmitt Input ( RESET 2 Schmitt Input Freescale Semiconductor Preliminary State During Reset Input, TC1 — Timer C, Channel 1 pull-up enabled Receive Data — SCI0 receive data input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TC1. ...
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... Peripheral User Manual. 28 Table 10-15. A recommended crystal oscillator circuit is shown EXTAL XTAL Sample External Crystal Parameters 750 KΩ Note: If the operating temperature range is limited to o below 85 CL2 56F8322 Techncial Data, Rev Meg Ω C (105 C junction), then R z Freescale Semiconductor Preliminary ...
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... Peripheral User Manual. 3.2.3 External Clock Source The recommended method of connecting an external clock is illustrated in source is connected to XTAL and the EXTAL pin is grounded. Figure 3-3 Connecting an External Clock Register Freescale Semiconductor Preliminary 3 Terminal Sample External Ceramic Resonator Parameters: EXTAL XTAL R = 750 KΩ ...
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... At reset, both oscillators will be powered up; however, the relaxation oscillator will be the default clock reference for the PLL. Software should power down the block not being used and program the PLL for the correct frequency. 30 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... Prescaler ÷ ( 3.5 Registers When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the register definitions with the internal Relaxation Oscillator, since the 56F8322 and 56F8122 contain this oscillator. Freescale Semiconductor Preliminary Relaxation OSC MUX PRECS ...
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... CDBW. Data Flash can be read via either CDBR or XDB2, but not by both simultaneously. None — None 8KB Erase / Program via Flash Interface unit and word 8KB writes to CDBW Table 4-2. The operating mode control bits (MA and MB) in the 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... Priority Peripheral Number Level core 2 3 core 3 3 core 4 3 core 5 3 Freescale Semiconductor Preliminary Memory Allocation RESERVED On-Chip Program RAM 4KB RESERVED Boot Flash 8KB Cop Reset Address = $02 0002 Boot Location = $02 0000 RESERVED Internal Program Flash 32KB Vector Base Address + ...
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... SPI 0 Transmitter Empty P:$54 SCI 1 Transmitter Empty P:$56 SCI 1Transmitter Idle Reserved P:$5A SCI 1 Receiver Error P:$5C SCI 1 Receiver Full Reserved P:$62 Quadrature Decoder #0 Home Switch or Watchdog P:$64 Quadrature Decoder #0 INDEX Pulse 56F8322 Techncial Data, Rev (Continued) Interrupt Function Freescale Semiconductor Preliminary ...
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... Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address the VBA is set to $0200, the first two locations of the vector table will overlay the chip reset addresses. Freescale Semiconductor Preliminary Vector Base ...
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... Memory chapter of the 56F8300 Peripheral User Manual. These configure parameters are located between $00_3FF7 and $00_3FFF. 36 Table 4-4 Data Memory Map Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED On-Chip Data Flash 8KB On-Chip Data RAM 2 8KB 56F8322 Techncial Data, Rev Freescale Semiconductor Preliminary ...
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... Flash memory block on the chip. Note: Data Flash is NOT available on the 56F8122 device. Flash Size Program Flash 32KB Data Flash Boot Flash Please see the 56F8300 Peripheral User Manual for additional Flash information. Freescale Semiconductor Preliminary 8KB Boot Reserved FM_PROG_MEM_TOP = $00_3FFF Configure Field Block 0 Odd ...
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... Instruction Step Counter Instruction Step Counter Control Register Reserved Core Lock / Unlock Status Register Transmit and Receive Status and Control Register Transmit Register / Receive Register Transmit Register Upper Word Receive Register Upper Word 56F8322 Techncial Data, Rev. 16 Register Name Freescale Semiconductor Preliminary ...
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... Power Supervisor FM FlexCAN Table 4-8 Quad Timer A Registers Address Map Register Acronym TMRA0_CMP1 TMRA0_CMP2 TMRA0_CAP TMRA0_LOAD TMRA0_HOLD TMRA0_CNTR TMRA0_CTRL TMRA0_SCR TMRA0_CMPLD1 Freescale Semiconductor Preliminary Prefix Base Address TMRA X:$00 F040 TMRC X:$00 F0C0 PWMA X:$00 F140 DEC0 X:$00 F180 ITCN X:$00 F1A0 ...
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... Compare Register 1 $31 Compare Register 2 $32 Capture Register $33 Load Register $34 Hold Register $35 Counter Register $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A Comparator Status and Control Register 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR TMRC3_CMP1 Freescale Semiconductor Preliminary (TMRC_BASE = $00 F0C0) Address Offset Register Description $0 Compare Register 1 $1 Compare Register 2 $2 Capture Register $3 Load Register $4 Hold Register $5 Counter Register $6 ...
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... Value Register 1 $8 Value Register 2 $9 Value Register 3 $A Value Register 4 $B Value Register 5 $C Dead Time Register $D Disable Mapping Register 1 $E Disable Mapping Register 2 $F Configure Register $10 Channel Control Register $11 Port Register $12 Internal Correction Control 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 Freescale Semiconductor Preliminary (DEC0_BASE = $00 F180) Address Offset Register Description $0 Decoder Control Register $1 Filter Interval Register $2 Watchdog Time-out Register $3 Position Difference Counter Register $4 Position Difference Counter Hold Register ...
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... Low Limit Register 0 $12 Low Limit Register 1 $13 Low Limit Register 2 $14 Low Limit Register 3 $15 Low Limit Register 4 $16 Low Limit Register 5 $17 Low Limit Register 6 $18 Low Limit Register 7 $19 High Limit Register 0 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... Temperature Sensor is NOT available in the 56F8122 device Register Acronym TSENSOR_CNTL Table 4-15 Serial Communication Interface 0 Registers Address Map Register Acronym SCI0_SCIBR SCI0_SCICR SCI0_SCISR SCI0_SCIDR Freescale Semiconductor Preliminary (ADCA_BASE = $00 F200) Address Offset Register Description $1A High Limit Register 1 $1B High Limit Register 2 $1C ...
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... Data Transmitter Register (SPI1_BASE = $00 F2B0) Address Offset Register Description $0 Status and Control Register $1 Data Size Register $2 Data Receive Register $3 Data Transmitter Register (COP_BASE = $00 F2C0) Address Offset Register Description $0 Control Register $1 Time-Out Register $2 Counter Register 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... GPIOA_PPMODE GPIOA_RAWDATA Table 4-22 GPIOB Registers Address Map Register Acronym GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR GPIOB_PPMODE GPIOB_RAWDATA Freescale Semiconductor Preliminary (CLKGEN_BASE = $00 F2D0) Address Offset Register Description $0 Control Register $1 Divide-By Register $2 Status Register Reserved $4 Shutdown Register $5 Oscillator Control Register ...
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... F360) Address Offset $0 Control Register $1 Status Register 56F8322 Techncial Data, Rev. 16 Reset Value 0 x 007C 0 x 0000 0 x 0000 0 x 007F 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 007F — Register Description Register Description Freescale Semiconductor Preliminary ...
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... FMOPT 1 FMOPT 2 Table 4-27 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8122 device Register Acronym FCMCR FCCTL0 FCCTL1 FCTMR FCMAXMB FCRXGMASK_H FCRXGMASK_L Freescale Semiconductor Preliminary (FM_BASE = $00 F400) Register Description $0 Clock Divider Register $1 Module Control Register Reserved $3 Security High Half Register $4 ...
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... Message Buffer 1 Data Register Reserved $50 Message Buffer 2 Control / Status Register $51 Message Buffer 2 ID High Register $52 Message Buffer 2 ID Low Register $53 Message Buffer 2 Data Register $54 Message Buffer 2 Data Register $55 Message Buffer 2 Data Register $56 Message Buffer 2 Data Register Reserved 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... FCMB5_DATA FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $58 Message Buffer 3 Control / Status Register $59 Message Buffer 3 ID High Register $5A Message Buffer 3 ID Low Register $5B Message Buffer 3 Data Register ...
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... Message Buffer 10 Data Register Reserved $98 Message Buffer 11 Control / Status Register $99 Message Buffer 11 ID High Register $9A Message Buffer 11 ID Low Register $9B Message Buffer 11 Data Register $9C Message Buffer 11 Data Register $9D Message Buffer 11 Data Register $9E Message Buffer 11 Data Register Reserved 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $A0 Message Buffer 12 Control / Status Register $A1 Message Buffer 12 ID High Register $A2 Message Buffer 12 ID Low Register $A3 Message Buffer 12 Data Register ...
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... Normal interrupt handling concatenates the VBA and the vector number to determine the vector address. In this way, an offset is generated into the vector table for each interrupt. 54 4-3, Interrupt Vector Table Contents. 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its fast interrupt handling. Freescale Semiconductor Preliminary 1 Permitted Exceptions ...
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... The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. 56 any0 Level 0 82 -> Priority Encoder any3 Level 3 82 -> Priority Encoder 56F8322 Techncial Data, Rev. 16 INT VAB CONTROL IPIC IACK SR[9:8] PIC_EN Freescale Semiconductor Preliminary ...
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... IRQP1 $12 IRQP2 $13 IRQP3 $14 IRQP4 $15 IRQP5 $16 ICTL $1D Freescale Semiconductor Preliminary Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F1A0) Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 ...
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... TMRA3 IPL TMRA2 IPL TMRA1 IPL IPL ADCA_ZC ADCA_CC IPL IPL 0 FAST INTERRUPT FAST INTERRUPT 0 VECTOR ADDRESS HIGH 0 FAST INTERRUPT FAST INTERRUPT 1 VECTOR ADDRESS HIGH IRQA INT_ STATE DIS Freescale Semiconductor 0 0 IRQA IPL 0 IPL IPL 0 1 PEND- ING [81] IRQA EDG Preliminary ...
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... IRQ is priority level 2 • IRQ is priority level 3 5.6.1.4 Reserved—Bits 9–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $ Read Write RESET Figure 5-4 Interrupt Priority Register 1 (IPR1) Freescale Semiconductor Preliminary STPCNT IPL ...
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... IRQ is priority level 2 • IRQ is priority level 3 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $ Read FMCBE IPL FMCC IPL Write RESET Figure 5-5 Interrupt Priority Register 2 (IPR2 FMERR IPL LOCK IPL LVI IPL 56F8322 Techncial Data, Rev IRQA IPL Freescale Semiconductor Preliminary 0 0 ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8322 Technical Data, Rev. 16 Register Descriptions 61 ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level FCMSGBUF IPL FCWKUP IPL 56F8322 Techncial Data, Rev FCERR IPL FCBOFF IPL Freescale Semiconductor Preliminary ...
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... IRQ is priority level 2 5.6.4.6 Reserved—Bits 1–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.5 Interrupt Priority Register 4 (IPR4) Base + $ Read SPI0_RCV SPI1_XMIT IPL Write RESET Figure 5-7 Interrupt Priority Register 4 (IPR4) Freescale Semiconductor Preliminary SPI1_RCV IPL IPL 56F8322 Technical Data, Rev ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 64 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary SCI1_RCV ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 66 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 56F8322 Techncial Data, Rev TMRC3 IPL TMRC2 IPL TMRC1 IPL Freescale Semiconductor Preliminary 0 0 ...
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... They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.9.3 Reserved—Bits 11–10 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary SCI0_TIDL SCI0_XMIT ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 70 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.10.4 Reserved—Bits 9–8 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary PWMA_RL ADCA_ZC IPL ...
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... The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt vector address. The lower eight bits of the ISR address are determined based upon the highest-priority interrupt; see VECTOR BASE ADDRESS Section 5.3.1 56F8322 Techncial Data, Rev for details. Freescale Semiconductor Preliminary 0 0 ...
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... Fast Interrupt 0 defined in the FIM0 register. 5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0) Base + $ Read Write RESET Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.14.1 Reserved—Bits 15–5 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary 4-3 ...
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... Fast Interrupt 1 defined in the FIM1 register. 5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1) Base + $ Read Write RESET Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1 4- FAST INTERRUPT 1 VECTOR ADDRESS LOW 56F8322 Techncial Data, Rev FAST INTERRUPT FAST INTERRUPT 1 VECTOR ADDRESS HIGH Freescale Semiconductor Preliminary ...
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... IRQ Pending (PENDING)—Bits 32–17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number Freescale Semiconductor Preliminary PENDING [16:2] ...
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... This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number PENDING [48:33 PENDING [64:49 PENDING [80:65 56F8322 Techncial Data, Rev Freescale Semiconductor Preliminary ...
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... IPIC Write RESET Figure 5-26 ITCN Control Register (ICTL) 5.6.30.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • interrupt is being sent to the 56800E core • interrupt is being sent to the 56800E core Freescale Semiconductor Preliminary ...
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... IRQA Edge Pin (IRQA Edg)—Bit 0 This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait modes automatically level-sensitive. • IRQA interrupt is a low-level sensitive (default) • IRQA interrupt is falling-edge sensitive 78 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... Pull-up enables for selected peripherals • System status registers • Registers for software access to the JTAG ID of the chip • Enforcing Flash security These are discussed in more detail in the sections that follow. Freescale Semiconductor Preliminary 56F8322 Technical Data, Rev. 16 Resets 79 ...
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... For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode. 80 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... SIM_SCR0 Base + $3 SIM_SCR1 Base + $4 SIM_SCR2 Base + $5 SIM_SCR3 Base + $6 SIM_MSH_ID Base + $7 SIM_LSH_ID Base + $8 SIM_PUDR Base + $A SIM_CLKOSR Base + $B SIM_GPS Base + $C SIM_PCE Base + $D SIM_ISALH Base + $E SIM_ISALL Freescale Semiconductor Preliminary R/W R Figure 6-1 OMR Table 6-1 SIM Registers (SIM_BASE = $00 F350) Register Name Control Register Reset Status Register ...
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... ADCA CAN DEC0 TMRC ISAL[21: 56F8322 Techncial Data, Rev ONCE SW STOP_ EBL0 RST DISABLE DISABLE SWR COPR EXTR POR JTAG CLK CLKOSEL DIS TMRA SCI1 SCI0 SPI1 SPI0 ISAL[23:22 ONCE SW STOP_ EBL0 RST DISABLE DISABLE Freescale Semiconductor 0 WAIT_ PWMA 0 WAIT_ 0 Preliminary ...
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... When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing this bit position will set the bit, while writing the bit will clear it. Freescale Semiconductor Preliminary 12 ...
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... This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (RESET pin, software reset, and COP reset FIELD 56F8322 Techncial Data, Rev Freescale Semiconductor Preliminary 0 0 ...
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... Write RESET Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR) 6.5.6.1 Reserved—Bits 15–12 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.2 RESET—Bit 11 This bit controls the pull-up resistors on the RESET pin. Freescale Semiconductor Preliminary ...
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... Peripheral output function of GPI B[7] is defined to be the oscillator clock (MSTR_OSC, see Figure 3-4) 6.5.7.3 PHASEB0 (PHSB)—Bit 8 • Peripheral output function of GPIOB[6] is defined to be PHASEB0 • Peripheral output function of GPIOB[6] is defined to be SYS_CLK2 PHSA PHSB INDEX HOME 56F8322 Techncial Data, Rev CLK CLKOSEL DIS Freescale Semiconductor Preliminary ...
Page 87
... SCI 0, or PWMA and SPI 1 are multiplexed, there are two possible peripherals as well as the GPIO functionality available for control of the I/O. The SIM_GPS register is used to determine which peripheral has control. The default peripherals are SPI 0, Quad Timer C, and PWMA. Note: PWM is NOT available in the 56F8122 device. Freescale Semiconductor Preliminary 56F8322 Technical Data, Rev. 16 Register Descriptions ...
Page 88
... This bit selects the alternate function for GPIOC6. • TC0 (default) • TXD0 6.5.8.3 GPIOC5 (C5)—Bit 6 This bit selects the alternate function for GPIOC5. • TC1 (default) • RXD0 88 GPIOX_PER Register GPIO Controlled 0 1 SIM_GPS Register 56F8322 Techncial Data, Rev. 16 I/O Pad Control Freescale Semiconductor Preliminary ...
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... The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip. Base + $ Read 1 1 ADCA Write RESET Figure 6-12 Peripheral Clock Enable Register (SIM_PCE) Freescale Semiconductor Preliminary CAN DEC0 TMRC 1 1 ...
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... This bit field is reserved or not implemented read as 1 and cannot be modified by writing. 6.5.9.9 Quad Timer A Enable (TMRA)—Bit 6 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 90 56F8322 Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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... If this register is set to something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected. Freescale Semiconductor Preliminary 56F8322 Technical Data, Rev. 16 Register Descriptions ...
Page 92
... This field represents the upper two address bits of the “hard coded” I/O short address. Base + $ Read Write RESET Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL) 92 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction ISAL[21: 56F8322 Techncial Data, Rev. 16 Instruction Portion ISAL[23:22 Freescale Semiconductor Preliminary ...
Page 93
... All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz. Refer to the PCE register in Section 6.5.9 frequency, which can be controlled through the OCCS. Freescale Semiconductor Preliminary Peripheral Clocks Active Device is fully functional Active Peripherals are active and can produce interrupts if they have not been masked off ...
Page 94
... After completion of the described reset sequence, application code will begin execution. Resets may be asserted asynchronously, but are always released internally on a rising edge of the system clock D-FLOP D-FLOP C R Note: Wait disable circuit is similar Reset 56F8322 Techncial Data, Rev. 16 56800E STOP_DIS Section 6.5.1 . This Freescale Semiconductor Preliminary ...
Page 95
... CPU. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability and access to the ID register. Freescale Semiconductor Preliminary 56F8322 Technical Data, Rev. 16 ...
Page 96
... SYS_CLK 2 FMCLKDIV JTAG FMERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. 96 Figure 7-1. FM_CLKDIV[6] will map to the Flash Memory input clock 7 FMCLKD 7 56F8322 Techncial Data, Rev. 16 DIVIDER 7 Freescale Semiconductor Preliminary ...
Page 97
... Flash with the original code, but modify the security bytes. To insure that a customer does not inadvertently lock himself out of the device during programming recommended that he program the backdoor access key first, his application code second and the security bytes within the FM configuration field last. Freescale Semiconductor Preliminary ( ) ...
Page 98
... Peripheral Function SPI 1 SPI 0, SCI1, TMRA XTAL, EXTAL, TMRC, SCI 0 56F8322 Techncial Data, Rev. 16 Reset Function PWM SPI 0, DEC 0 XTAL, EXTAL, CAN, TMRC Reset Function Must be reconfigured SPI 0, other pins must be reconfigured XTAL, EXTAL, TMRC; other pins must be reconfigured Freescale Semiconductor Preliminary ...
Page 99
... GPIOB2 MOSI0 GPIOB3 SCLK0 GPIOB4 HOME0 / TA3 GPIOB5 INDEX0 / TA2 GPIOB6 PHASEB0 / TA1 Freescale Semiconductor Preliminary Package Pin 3 PWM is NOT available in 56F8122 4 PWM is NOT available in 56F8122 6 SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis PWM is NOT available in 56F8122 ...
Page 100
... SCI0 on a pin-by-pin basis 1 SIM register SIM_GPS is used to select between Timer C and SCI0 on a pin-by-pin basis 4-21 through 4-23 marketing representative DD 56F8322 Techncial Data, Rev. 16 Notes define the actual reset values of or authorized distributor in the package. Freescale Semiconductor Preliminary for ...
Page 101
... However, normal precautions are advised to avoid application maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Freescale Semiconductor Preliminary are stress ratings only, and functional operation at the maximum CAUTION of any voltages higher 56F8322 Technical Data, Rev ...
Page 102
... GPIO pins used in open OD drain mode STG T STG 56F8322 Techncial Data, Rev. 16 Min Max Unit - 0.3 4 0.3 4 0.3 4 0.3 3.0 V -0.3 6.0 V -0.3 4.0 V -0.3 4 6.0 -0.3 6.0 V -40 125 °C -40 105 °C -40 150 °C -40 125 °C -55 150 °C -55 150 °C Freescale Semiconductor Preliminary ...
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... Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. See Section 12.1 for more details on thermal design considerations Junction temperature TA = Ambient temperature Freescale Semiconductor Preliminary Min 2000 200 500 Table 10-3 Thermal Characteristics ...
Page 104
... V +0.3 DDA DDA 2 — V +0.3 DDA -0.3 — 0.8 — — -4 — — -12 — — 4 — — 12 -40 — 125 -40 — 105 10,000 — — Cycles 10,000 — — Cycles 15 — — Years Freescale Semiconductor Preliminary Unit MHz °C °C ...
Page 105
... HYS Hysteresis Input Capacitance C INC (EXTAL/XTAL) Output Capacitance C OUTC (EXTAL/XTAL) Input Capacitance C IN Output Capacitance C OUT See Pin Groups in Table 10-1 Freescale Semiconductor Preliminary Table 10-4 Notes Min Typ 2.4 — — — Pin Groups — Pin Group Pin Group 7 — ...
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... Relaxation oscillator is off 0μA 145μA • All peripheral clocks are off • ADC powered off • PLL powered off 56F8322 Techncial Data, Rev. 16 Typ Max Units — — V 1.8 1.9 V 2.14 — V 2.7 — V μA 110 130 Test Conditions Freescale Semiconductor Preliminary ...
Page 107
... The second regulator supplies approximately 2.6V to the device’s core logic. This regulator μ requires two external 2 greater, capacitors for proper operation. Ceramic and tantalum capacitors tend to provide better performance tolerances. The output voltage can be measured directly on the V pins. The specifications for this regulator are shown in Freescale Semiconductor Preliminary ...
Page 108
... RS T 120 PV T — — BIAS I — PD 56F8322 Techncial Data, Rev. 16 Typical Max Unit — 2.75 V — 2.75 V — 2.75 V — 700 mA 5 μ — 30 minutes Typical Max Unit 0 0. — 200 ps — 175 ps 1 μA 100 150 Freescale Semiconductor Preliminary ...
Page 109
... Input Signal Midpoint1 Fall Time Note: The midpoint Figure 10-1 Input Signal Measurement References Freescale Semiconductor Preliminary Symbol Min m — ...
Page 110
... Flash memories, increasing the effective page size to 1024 bytes. 110 Data2 Valid Data2 Data Tri-stated Figure 10-2 Signal States Symbol Min T 20 prog T 20 erase T 100 me 56F8322 Techncial Data, Rev. 16 and Data3 Valid Data3 Data Active Typ Max Unit μs — — — — ms — — ms Freescale Semiconductor Preliminary ...
Page 111
... An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f 56F8300 Peripheral User Manual. 3. This is the minimum time required after the PLL set up is changed to ensure reliable operation. Freescale Semiconductor Preliminary Symbol 2 f — ...
Page 112
... Techncial Data, Rev. 16 Typ Max Unit 0. — 120 ohms — 250 ps — 1.5 ns — 300 ps — 300 ps μA 250 290 μA 80 110 μ Max Units — MHz — ps — /-3 % 500 ps μs 4 Freescale Semiconductor Preliminary ...
Page 113
... IRQA Width Assertion to Recover from Stop State 1. In the formulas clock cycle. For an operating frequency of 60MHz 16.67ns. At 8MHz (used during Reset and Stop modes 125ns. 2. Parameters listed are guaranteed by design. 3. The interrupt instruction fetch is visible on the pins only in Mode 3. Freescale Semiconductor Preliminary Typical Response + ...
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... IRQA PAB Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing 114 IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I 56F8322 Techncial Data, Rev RDA First Fetch First Instruction Fetch Not IRQA Interrupt Vector Freescale Semiconductor Preliminary ...
Page 115
... Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. Freescale Semiconductor Preliminary 1 Table 10-18 SPI Timing Symbol Min ELD — ELG — ...
Page 116
... SS is held High on master MSB in Bits 14– Master MSB out Bits 14– held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8322 Techncial Data, Rev LSB in (ref Master LSB out LSB in t (ref Master LSB out t R Freescale Semiconductor Preliminary ...
Page 117
... SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-11 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output) MOSI (Input) Figure 10-12 SPI Slave Timing (CPHA = 1) Freescale Semiconductor Preliminary ELD Slave MSB out Bits 14– ...
Page 118
... P P OUTHL OUT Figure 10-13 Timer Timing Symbol Min 56F8322 Techncial Data, Rev Max Unit See Figure — ns 10-13 — ns 10-13 — ns 10-13 — ns 10-13 P INHL P OUTHL 1, 2 Max Unit See Figure — ns 10-14 — ns 10-14 — ns 10-14 Freescale Semiconductor Preliminary ...
Page 119
... The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. RXD SCI receive data pin (Input) TXD SCI receive data pin (Input) Freescale Semiconductor Preliminary ...
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... Table 10-23 JTAG Timing Symbol Min f DC SYS_CLK SYS_CLK — — TS 56F8322 Techncial Data, Rev Max Unit See Figure 1 Mbps μs — Max Unit See Figure MHz 10-18 MHz 10-18 — ns 10-18 — ns 10-19 — ns 10- 10- 10-19 Freescale Semiconductor — 10-17 Preliminary ...
Page 121
... TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-19 Test Access Port Timing Diagram 10.15 Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity Monotonicity ADC internal clock Conversion range Freescale Semiconductor Preliminary 1 )/ Input Data Valid ...
Page 122
... See Figure 10-20 — 0.008597 — -2.8 — -60 — — REFH REFLO 64.6 — 59.1 — 60.6 — 61.1 — 9.6 — Freescale Semiconductor Unit 3 cycles ms 3 cycles 3 cycles μA — mV LSBs — — Bits Preliminary ...
Page 123
... Although not guaranteed believed that calibration will produce results similar to those shown above for any population of parts, including those which represent processing and temperature extremes. Freescale Semiconductor Preliminary = 0.60V and 2.70V in 56F8322 Technical Data, Rev ...
Page 124
... These include RAM, Flash memory and the ADCs. 124 )/2, while the other charges to the analog input voltage. When the REFH REFLO ) 56F8322 Techncial Data, Rev )/2. The switches switch REFH REFLO 1pF Freescale Semiconductor Preliminary ...
Page 125
... For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. Freescale Semiconductor Preliminary 2 *F CMOS power dissipation corresponding to the is tied to V inside this package ...
Page 126
... Figure 11-1 Top View, 56F8322 48-Pin LQFP Package 126 Figure 11-1 shows the package outline for the 48-pin LQFP, ORIENTATION MARK 56F8322 Techncial Data, Rev. 16 Table 11-1 lists the pin-out for the INDEX0 HOME0 V DD_IO XTAL EXTAL DDA_ADC V SSA_ADC V REFP V REFMID V REFN ANA6 Freescale Semiconductor Preliminary ...
Page 127
... RESET 14 3 PWMA0 15 4 PWMA1 DD_IO 6 PWMA2 18 7 PWMA3 19 8 PWMA4 20 9 PWMA5 IRQA 23 12 FAULTA0 24 Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name V 25 ANA6 DD_IO REFN SS0 27 V REFMID MISO0 28 V REFP CAP SSA_ADC MOSI0 30 V DDA_ADC SCLK0 31 V ANA0 ...
Page 128
... Figure 11-2 Top View, 56F8122 48-Pin LQFP Package 128 Figure 11-1 shows the package outline for the 48-pin LQFP, ORIENTATION MARK 56F8322 Techncial Data, Rev. 16 Table 11-1 lists the pin-out for the TA2 TA3 V DD_IO XTAL EXTAL DDA_ADC V SSA_ADC V REFP V REFMID V REFN ANA6 Freescale Semiconductor Preliminary ...
Page 129
... RESET 14 3 GPIOA0 15 4 GPIOA1 DD_IO 6 SS1 18 7 MISO1 19 8 MOSI1 20 9 SCLK1 IRQA 23 12 GPIOA6 24 Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name V 25 ANA6 DD_IO REFN SS0 27 V REFMID MISO0 28 V REFP CAP SSA_ADC MOSI0 30 V DDA_ADC SCLK0 31 V ANA0 ...
Page 130
... E 1.350 1.450 F 0.170 0.230 G 0.500 BSC H 0.050 0.150 J 0.090 0.200 K 0.500 0.700 ° ° ° REF N 0.090 0.160 P 0.250 BSC R 0.150 0.250 S 9.000 BSC S1 4.500 BSC V 9.000 BSC V1 4.500 BSC W 0.200 REF AA 1.000 REF R L ° Freescale Semiconductor Preliminary ...
Page 131
... D where Thermocouple temperature on top of package ( T Ψ = Thermal characterization parameter ( Power dissipation in package (W) D Freescale Semiconductor Preliminary , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with a JT ...
Page 132
... Ceramic and tantalum capacitors tend to provide better DDA SSA. layers of the PCB with approximately 100μF, preferably with a high-grade 56F8322 Techncial Data, Rev. 16 higher than pin on the device and from the DD and V (GND and Freescale Semiconductor Preliminary ...
Page 133
... Flash, RAM and internal logic are powered from the core regulator output • and V 2 are not connected in the customer system PP PP • All circuitry, analog and digital, shares a common V V DDA_OSC_PLL REG OCS ROSC Freescale Semiconductor Preliminary , V REF DDA pins. bus CAP REG CORE ...
Page 134
... Techncial Data, Rev. 16 Temperature Order Number (MHz) Range 60 -40° 105° C MC56F8322VFA60 60 -40° 125° C MC56F8322MFA60 40 -40° 105° C MC56F8122VFA 60 -40° 105° C MC56F8322VFAE* 60 -40° 125° C MC56F8322MFAE* 40 -40° 105° C MC56F8122VFAE* Freescale Semiconductor Preliminary ...
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... Freescale Semiconductor Preliminary 56F8322 Technical Data, Rev. 16 Power Distribution and I/O Ring Implementation 135 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...