MCF51EM256CLK Freescale Semiconductor, MCF51EM256CLK Datasheet - Page 94

• Manufacturer Part Number: MCF51EM256CLK
• Description: IC MCU 32BIT 256KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Memory
3.4.4.2
The flash command controller is used to supervise the command write sequence to execute program, erase,
and erase verify algorithms.
Before starting a command write sequence, the FACCERR and FPVIOL flags in the FxSTAT register must
be clear and the FCBEF flag must be set (see
A command write sequence consists of three steps which must be strictly adhered to with writes to the flash
module not permitted between the steps. However, flash register and array reads are allowed during a
command write sequence. The basic command write sequence is as follows:
Once a command is launched, the completion of the command operation is indicated by the setting of the
FCCF flag in the FxSTAT register. The FCCF flag will set upon completion of all active and buffered burst
program commands.
3.4.5
Table 3-14
block.
3.4.5.1
The erase verification operation will verify that the entire flash array memory is erased.
3-38
1. Write to a valid address in the flash array memory.
2. Write a valid command to the FxCMD register.
3. Clear the FCBEF flag in the FxSTAT register by writing a 1 to FCBEF to launch the command.
FCMD
0x05
0x20
0x25
0x40
0x41
summarizes the valid flash commands along with the effects of the commands on the flash
Flash Commands
Command Write Sequence
Erase Verification Command
Burst Program
Sector Erase
Erase Verify
Mass Erase
A flash block address must be in the erased state before being programmed.
Cumulative programming of bits within a flash block address is not allowed
except for status field updates required in EEPROM emulation applications.
Command
Program
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
NVM
Verify all memory bytes in the flash array memory are erased.
If the flash array memory is erased, the FBLANK flag in the FxSTAT register will set upon
command completion.
Program an address in the flash array.
Program an address in the flash array with the internal address incrementing after the
program operation.
Erase all memory bytes in a sector of the flash array.
Erase all memory bytes in the flash array.
A mass erase of the full flash array is only possible when no protection is enabled prior
to launching the command.
Table 3-14. Flash Command Description
Section
CAUTION
Function on Flash Memory
3.4.3.5).
Freescale Semiconductor