C8051F019-GQ Silicon Laboratories Inc, C8051F019-GQ Datasheet - Page 88

• Manufacturer Part Number: C8051F019-GQ
• Description: IC 8051 MCU 16K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F018r

Specifications of C8051F019-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• No. Of I/o's: 16
• Ram Memory Size: 1.25KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1198

In the Priority Decode Table, a dot () is used to show the external Port I/O pin (column) to which each signal (row)
can be assigned by the user application code via programming registers XBR2, XBR1, and XBR0.
SDA
SCL
SCK
MISO
MOSI
NSS
TX
RX
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
CP0
CP1
T0
/INT0
T1
/INT1
T2
T2EX
/SYSCLK
CNVSTR
PIN I/O 0




             
              
               
                
                 
                  
                   
                    
                     
                      
                       




1





2





3
P0





4




5
Table 13.1. Crossbar Priority Decode




6



7



0


1
Rev. 1.2


2

3
P1

4
5
6
7
0
1
2
C8051F018
C8051F019
3
P2
4
5
6
7
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